Jochen A. G. Jess

Publication Activity (10 Years)

Years Active: 1982-2006
Publications (10 Years): 0

Publications

Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Jochen A. G. Jess
Codeübersetzung unter Zeitvorgaben für eingebettete Signalprozessoren (Performance Controlled Compilation for Embedded Signal Processors). it Inf. Technol. 45 (6) (2003)
Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
Statistical timing for parametric yield prediction of digital integrated circuits. DAC (2003)
Jochen A. G. Jess
Parametric Yield Estimation for Deep Sub- Micron VLSI Circuits. SBCCI (2002)
Qin Zhao, Twan Basten, Bart Mesman, C. A. J. van Eijk, Jochen A. G. Jess
Static resource models of instruction sets. ISSS (2001)
Carlos A. Alba Pinto, Bart Mesman, Koen van Eijk, Jochen A. G. Jess
Constraint satisfaction for storage files with Fifos or stacks during scheduling. DATE (2001)
Marco Bekooij, Jochen A. G. Jess, Jef L. van Meerbergen
Phase coupled operation assignment for VLIW processors with distributed register files. ISSS (2001)
Carlos A. Alba Pinto, Bart Mesman, Jochen A. G. Jess
Constraint Satisfaction for Relative Location Assignment and Scheduling. ICCAD (2001)
Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess
Prophid: A Platform-Based Design Method. Des. Autom. Embed. Syst. 6 (1) (2000)
Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, J. Van Eijnhoven, Jochen A. G. Jess
A code-motion pruning technique for global scheduling. ACM Trans. Design Autom. Electr. Syst. 5 (1) (2000)
Jochen A. G. Jess
Designing electronic engines with electronic engines: 40 years ofbootstrapping of a technology upon itself. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (12) (2000)
Qin Zhao, C. A. J. van Eijk, Carlos A. Alba Pinto, Jochen A. G. Jess
Register Binding for Predicated Execution in DSP Applications. SBCCI (2000)
Carlos A. Alba Pinto, Koen van Eijk, Bart Mesman, Jochen A. G. Jess
Address Satisfaction for Storage Files with Fifos or Stacks during Scheduling of DSP Algorithms. SBCCI (2000)
Koen van Eijk, Bart Mesman, Carlos A. Alba Pinto, Qin Zhao, Marco Bekooij, Jef L. van Meerbergen, Jochen A. G. Jess
Constraint analysis for code generation: basic techniques and applications in FACTS. ACM Trans. Design Autom. Electr. Syst. 5 (4) (2000)
Luiz C. V. dos Santos, Jochen A. G. Jess
A Reordering Technique for Efficient Code Motion. DAC (1999)
Bart Mesman, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
Constraint analysis for DSP code generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (1) (1999)
Luiz C. V. dos Santos, Jochen A. G. Jess
Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation. DATE (1999)
Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess
Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor. DATE (1998)
Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
A Constraint Driven Approach to Loop Pipelining and Register Binding. DATE (1998)
Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess
PROPHID: a data-driven multi-processor architecture for high-performance DSP. ED&TC (1997)
Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess
PROPHID: A Heterogeneous Multi-Processor Architecture for Multimedia. ICCD (1997)
Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
Constraint Analysis for DSP Code Generation. ISSS (1997)
Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess
Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (11) (1996)
C. A. J. van Eijk, Jochen A. G. Jess
Exploiting Functional Dependencies in Finite State Machine Verification. ED&TC (1996)
Chennian Di, Jochen A. G. Jess
An efficient CMOS bridging fault simulator: with SPICE accuracy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (9) (1996)
Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, Jos T. J. van Eijndhoven, Jochen A. G. Jess
A Constructive Method for Exploiting Code Motion. ISSS (1996)
Marino T. J. Strik, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess, Stefaan Note
Efficient code generation for in-house DSP-cores. ED&TC (1995)
Adwin H. Timmer, Jochen A. G. Jess
Exact scheduling strategies based on bipartite graph matching. ED&TC (1995)
Adwin H. Timmer, Marino T. J. Strik, Jef L. van Meerbergen, Jochen A. G. Jess
Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores. DAC (1995)
Marc J. M. Heijligers, L. J. M. Cluitmans, Jochen A. G. Jess
High-level synthesis scheduling and allocation using genetic algorithms. ASP-DAC (1995)
Jeroen A. J. Leijten, Jef L. van Meerbergen, Jochen A. G. Jess
Analysis and reduction of glitches in synchronous networks. ED&TC (1995)
J. W. G. Fleurkens, C. A. J. van Eijk, Jochen A. G. Jess
Run-time consistency checking in discrete simulation models. ED&TC (1995)
Hua Xue, Ed P. Huijbregts, Jochen A. G. Jess
Routing for Manufacturability. DAC (1994)
Ed P. Huijbregts, Jos T. J. van Eijndhoven, Jochen A. G. Jess
On Design Rule Correct Maze Routing. EDAC-ETC-EUROASIC (1994)
Hua Xue, Chennian Di, Jochen A. G. Jess
Probability Analysis for CMOS Floating Gate Faults. EDAC-ETC-EUROASIC (1994)
Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess
Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. ICCAD (1994)
M. J. M. Heijiligers, H. A. Hilderink, Adwin H. Timmer, Jochen A. G. Jess
NEAT: An Object Oriented High-Level Synthesis Interface. ISCAS (1994)
Hua Xue, Chennian Di, Jochen A. G. Jess
Fast Multi-Layer Critical Area Computation. DFT (1993)
Ed P. Huijbregts, Jochen A. G. Jess
A Multiple Terminal Net Routing Algorithm Using Failure Prediction. VLSI Design (1993)
Adwin H. Timmer, Jochen A. G. Jess
Execution interval analysis under resource constraints. ICCAD (1993)
M. M. A. van Rosmalen, Keith Baker, Eric Bruls, Jochen A. G. Jess
Parameter Monitoring: Advantages and Pitfalls. ITC (1993)
Chennian Di, Jochen A. G. Jess
On CMOS bridge fault modeling and test pattern evaluation. VTS (1993)
Hua Xue, Chennian Di, Jochen A. G. Jess
A net-oriented method for realistic fault analysis. ICCAD (1993)
Ed P. Huijbregts, Jochen A. G. Jess
General gate array routing using a k-terminal net routing algorithm with failure prediction. IEEE Trans. Very Large Scale Integr. Syst. 1 (4) (1993)
Chennian Di, Jochen A. G. Jess
On Accurate Modeling and Efficient Simulation of CMOS Opens. ITC (1993)
Leon Stok, Jochen A. G. Jess
Foreground memory management in data path synthesis. Int. J. Circuit Theory Appl. 20 (3) (1992)
Eric Bruls, F. Camerik, H. J. Kretschman, Jochen A. G. Jess
A Generic Method to Develop a Defect Monitoring System for IC Processes. ITC (1991)
Michel R. C. M. Berkelaar, Jochen A. G. Jess
Gate sizing in MOS digital circuits with linear programming. EURO-DAC (1990)
José Pineda de Gyvez, Jochen A. G. Jess
On the design and implementation of a wafer yield editor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (8) (1989)
José Pineda de Gyvez, Jochen A. G. Jess
A layout defect-sensitivity extractor. ICCAD (1989)
F. Camerik, P. A. J. Dirks, Jochen A. G. Jess
Qualification and Quantification of Process-Induced Product-Related Defects. ITC (1989)
Michel R. C. M. Berkelaar, Jochen A. G. Jess
Technology mapping for standard-cell generators. ICCAD (1988)
Jochen A. G. Jess, H. G. M. Kees
Decomposition. IEEE Trans. Computers 31 (3) (1982)