Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator.
Michel R. C. M. BerkelaarPim H. W. BuurmanJochen A. G. JessPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1996)
Keyphrases
- piecewise linear
- power consumption
- power dissipation
- low power
- cmos technology
- nm technology
- end to end delay
- energy efficiency
- power management
- dynamic programming
- energy saving
- chaotic map
- power saving
- hyperplane
- smooth curves
- battery life
- battery powered
- high speed
- data center
- principal curves
- power reduction
- real time
- low power consumption
- image processing
- mobile devices