Michel R. C. M. Berkelaar

Publication Activity (10 Years)

Years Active: 1988-2004
Publications (10 Years): 0

Publications

Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. ICCD (2004)
Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning. MBMV (2004)
Michel R. C. M. Berkelaar, Koen van Eijk
Efficient and Effective Redundancy Removal for Million-Gate Circuits. DATE (2002)
E. T. A. F. Jacobs, Michel R. C. M. Berkelaar
Gate Sizing Using a Statistical Delay Model. DATE (2000)
J. W. J. M. Rutten, Michel R. C. M. Berkelaar, C. A. J. van Eijk, M. A. J. Kolsteren
An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization. DATE (1998)
J. W. J. M. Rutten, Michel R. C. M. Berkelaar
Efficient exact and heuristic minimization of hazard-free logic. ICCD (1998)
Harm Arts, Michel R. C. M. Berkelaar, Koen van Eijk
Computing observability don't cares efficiently through polarization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (7) (1998)
J. W. J. M. Rutten, Michel R. C. M. Berkelaar
Improved State Assignment for Burst Mode Finite State Machines. ASYNC (1997)
Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess
Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (11) (1996)
Harm Arts, Michel R. C. M. Berkelaar, C. A. J. van Eijk
Polarized observability don't cares. ICCAD (1996)
Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken
Efficient orthonormality testing for synthesis with pass-transistor selectors. ICCAD (1995)
Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, Shiv Prakash
Efficient use of large don't cares in high-level and logic synthesis. ICCAD (1995)
Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess
Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator. ICCAD (1994)
Michel R. C. M. Berkelaar, Jochen A. G. Jess
Gate sizing in MOS digital circuits with linear programming. EURO-DAC (1990)
Michel R. C. M. Berkelaar, Jochen A. G. Jess
Technology mapping for standard-cell generators. ICCAD (1988)