Leon Stok

Publication Activity (10 Years)

Years Active: 1989-2023
Publications (10 Years): 5

Top Topics

Technical Challenges

Structure Extraction

Quantum Computing

Top Venues

Publications

Leon Stok
Quantum Challenges for EDA. ISPD (2023)
Sherief Reda, Leon Stok, Pierre-Emmanuel Gaillardon
Guest Editors' Introduction: The Resurgence of Open- Source EDA Technology. IEEE Des. Test 38 (2) (2021)
Leon Stok
EDA and Quantum Computing: The key role of Quantum Circuits. ISPD (2021)
Shesha Raghunathan, Leon Stok
EDA and Quantum Computing: a symbiotic relationship? IEEE Des. Test 37 (6) (2020)
Leon Stok
Concurrent High Performance Processor Design: From Logic to PD in Parallel. ISPD (2018)
Leon Stok
The Next 25 Years in EDA: A Cloudy Future? IEEE Des. Test 31 (2) (2014)
Leon Stok
Developing Parallel EDA Tools [The Last Byte]. IEEE Des. Test 30 (1) (2013)
Ruchir Puri, William H. Joyner, Raj Jammy, Ahmed Jerraya, Jan M. Rabaey, Walden C. Rhines, Leon Stok
EDA challenges and options: investing for the future. DAC (2010)
Leon Stok
From restrictive to prescriptive design. ASP-DAC (2009)
Leon Stok
Variability and New Design Paradigms. IEEE Des. Test Comput. 25 (4) (2008)
Sachin S. Sapatnekar, Leon Stok
DAC Highlights. IEEE Des. Test Comput. 24 (5) (2007)
Ruchir Puri, Leon Stok, Subhrajit Bhattacharya
Keeping hot chips cool. DAC (2005)
Ruchir Puri, David S. Kung, Leon Stok
Minimizing power with flexible voltage islands. ISCAS (1) (2005)
Leon Stok, John M. Cohn
There is life left in ASICs. ISPD (2003)
Soha Hassoun, Steven M. Nowick, Leon Stok
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (6) (2003)
Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni
Pushing ASIC performance in a power envelope. DAC (2003)
Thomas Kutzschebauch, Leon Stok
Layout Driven Decomposition with Congestion Consideration. DATE (2002)
Thomas Kutzschebauch, Leon Stok
Congestion Aware Layout Driven Logic Synthesis. ICCAD (2001)
Raul Camposano, Olivier Coudert, Patrick Groeneveld, Leon Stok, Ralph H. J. M. Otten
Timing closure: the solution and its problems. ASP-DAC (2000)
Thomas Kutzschebauch, Leon Stok
Regularity Driven Logic Synthesis. ICCAD (2000)
Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty
Transformational Placement and Synthesis. DATE (2000)
Frederik Beeftink, Prabhakar Kudva, David S. Kung, Ruchir Puri, Leon Stok
Combinatorial cell design for CMOS libraries. Integr. 29 (1) (2000)
Leon Stok, Andrew J. Sullivan, Mahesh A. Iyer
Wavefront Technology Mapping. DATE (1999)
Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok
Don't cares in synthesis: theoretical pitfalls and practical solutions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (4) (1998)
Frederik Beeftink, Prabhakar Kudva, David S. Kung, Leon Stok
Gate-size selection for standard cell libraries. ICCAD (1998)
Anirudh Devgan, Leon Stok, Sandip Kundu
Timing analysis and optimization: from devices to systems (tutorial). ICCAD (1997)
Guy Even, Ilan Y. Spillinger, Leon Stok
Retiming revisited and reversed. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (3) (1996)
Leon Stok, David S. Kung, Daniel Brand, Anthony D. Drumm, Andrew J. Sullivan, Lakshmi N. Reddy, Nathaniel Hieter, David J. Geiger, Han Hsun Chao, Peter J. Osler
BooleDozer: Logic synthesis for ASICs. IBM J. Res. Dev. 40 (4) (1996)
Daniel Brand, Reinaldo A. Bergamaschi, Leon Stok
Be careful with don't cares. ICCAD (1995)
Reinaldo A. Bergamaschi, Richard A. O'Connor, Leon Stok, Michael Z. Moricz, Shiv Prakash, Andreas Kuehlmann, D. Sreenivasa Rao
High-level synthesis in an industrial environment. IBM J. Res. Dev. 39 (1-2) (1995)
Leon Stok, Ilan Y. Spillinger, Guy Even
Improving initialization through reversed retiming. ED&TC (1995)
Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, Shiv Prakash
Efficient use of large don't cares in high-level and logic synthesis. ICCAD (1995)
Leon Stok
Data path synthesis. Integr. 18 (1) (1994)
Leon Stok
Is high-level synthesis marketable? (panel). HLSS (1994)
Leon Stok, Jochen A. G. Jess
Foreground memory management in data path synthesis. Int. J. Circuit Theory Appl. 20 (3) (1992)
Leon Stok
False loops through resource sharing. ICCAD (1992)
H. M. A. M. Arts, Jos T. J. van Eijndhoven, Leon Stok
Flexible Block-Multiplier Generation. ICCAD (1991)
Leon Stok
Interconnect optimisation during data path allocation. EURO-DAC (1990)
Leon Stok, G. P. Koster
From Network to Artwork. DAC (1989)