Ilan Y. Spillinger

Publication Activity (10 Years)

Years Active: 1986-2000
Publications (10 Years): 0

Publications

Ilan Y. Spillinger, Chris J. Newburn
Guest Editors' Introduction. J. Instr. Level Parallelism 2 (2000)
Guy Even, Ilan Y. Spillinger, Leon Stok
Retiming revisited and reversed. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (3) (1996)
Leon Stok, Ilan Y. Spillinger, Guy Even
Improving initialization through reversed retiming. ED&TC (1995)
Gabriel M. Silberman, Ilan Y. Spillinger
A backtracing-oriented procedure for the analysis of combinational gate-level designs. Integr. 17 (3) (1994)
Gideon D. Intrater, Ilan Y. Spillinger
Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers. IEEE Trans. Computers 43 (10) (1994)
Guy Even, Ophir Rachman, Ilan Y. Spillinger
Linear test sequences for detecting functionally faulty RAM's. Integr. 16 (1) (1993)
Shlomit Weiss, Ilan Y. Spillinger, Gabriel M. Silberman
Architectural Improvement for a Data-Driven VLSI Processing Array. J. Parallel Distributed Comput. 19 (4) (1993)
Gideon D. Intrater, Ilan Y. Spillinger
Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers. ISCA (1992)
Gabriel M. Silberman, Ilan Y. Spillinger
Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation. IEEE Trans. Computers 40 (1) (1991)
Gabriel M. Silberman, Ilan Y. Spillinger
RIDDLE: A Foundation for Test Generation on a High-Level Design Description. IEEE Trans. Computers 40 (1) (1991)
Gabriel M. Silberman, Ilan Y. Spillinger
Using functional fault simulation and the difference fault model to estimate implementation fault coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (12) (1990)
Shlomit Weiss, Ilan Y. Spillinger, Gabriel M. Silberman
Architectural Improvements for Data-Driven VLSI Processing Arrays. FPCA (1989)
Raphael Renous, Gabriel M. Silberman, Ilan Y. Spillinger
Whistle: A Workbench for Test Development of Library-Based Designs. Computer 22 (4) (1989)
Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger
Delay Test Generation 1: Concepts and Coverage Metrics. ITC (1988)
Gabriel M. Silberman, Ilan Y. Spillinger
G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing. ITC (1988)
Vijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger
Delay Test Generation 2: Algebra and Algorithms. ITC (1988)
Gabriel M. Silberman, Ilan Y. Spillinger
RIDDLE: a foundation for test generation on a high level design description. FTCS (1988)
Gabriel M. Silberman, Ilan Y. Spillinger
The Difference Fault Model : Using Functional Fault Simulation to Obtain Implementation Fault Coverage. ITC (1986)
Ilan Y. Spillinger, Gabriel M. Silberman
Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 (3) (1986)