HLSS

Keyphrases

Publications

1994

Giovanni Mancini
Hardware/software co-verification in ATM. HLSS (1994)
Michael Sheliga, Edwin Hsing-Mean Sha
Global node reduction of linear systems using ratio analysis. HLSS (1994)
Ravibala Singh, John Knight
Concurrent testing in high-level synthesis. HLSS (1994)
Peter Marwedel
ASICs vs ASIPs (panel). HLSS (1994)
Leon Stok
Is high-level synthesis marketable? (panel). HLSS (1994)
Koen Schoofs, Gert Goossens, Hugo De Man
Bit-alignment for retargetable code generators. HLSS (1994)
Marco A. Escalante, Nikitas J. Dimopoulos
Timing analysis for synthesis in microprocessor interface design. HLSS (1994)
Roger P. Ang, Nikil D. Dutt
An algorithm for the allocation of functional units from realistic RT component libraries. HLSS (1994)
F. Kenneth Zadeck
State-of-the-art compiler optimization. HLSS (1994)
Ruchir Puri, Jun Gu
A divide-and-conquer approach for asynchronous interface synthesis. HLSS (1994)
Steve C.-Y. Huang, Wayne H. Wolf
How datapath allocation affects controller delay. HLSS (1994)
Ramesh Karri, Karin Högstedt, Alex Orailoglu
Rapid prototyping of fault-tolerant VLSI systems. HLSS (1994)
Asawaree Kalavade, Edward A. Lee
A methodology for simulation and synthesis of mixed hardware/software systems. HLSS (1994)
Johan Van Praet, Gert Goossens, Dirk Lanneer, Hugo De Man
Instruction set definition and instruction selection for ASIPs. HLSS (1994)
Doron Mintz, Carlos Dangelo
Timing estimation for behavioral descriptions. HLSS (1994)
Lawrence F. Arnstein, Donald E. Thomas
Applications of attributed-behavior synthesis. HLSS (1994)
D. Sreenivasa Rao, Fadi J. Kurdahi
Controller and datapath trade-offs in hierarchical RT-level synthesis. HLSS (1994)
Prabhakar Kudva, Venkatesh Akella
Testing two-phase transition signaling based self-timed circuits in a synthesis environment. HLSS (1994)
Chih-Tung Chen, Alice C. Parker
A hybrid numeric/symbolic program for checking functional and timing compatibility of synthesized designs. HLSS (1994)
Pravil Gupta, Alice C. Parker
SMASH: a program for scheduling memory-intensive application-specific hardware. HLSS (1994)
Martin Janssen, Francky Catthoor, Hugo De Man
A specification invariant technique for operation cost minimisation in flow-graphs. HLSS (1994)
Rainer Leupers, Wolfgang Schenk, Peter Marwedel
Retargetable assembly code generation by bootstrapping. HLSS (1994)
Samit Chaudhuri, Robert A. Walker
Computing lower bounds on functional units before scheduling. HLSS (1994)
Dirk Lanneer, Marco Cornero, Gert Goossens, Hugo De Man
Data routing: a paradigm for efficient data-path synthesis and code generation. HLSS (1994)
Wei-Kai Cheng, Youn-Long Lin
Code generation for a DSP processor. HLSS (1994)
Albert van der Werf, Jef L. van Meerbergen, Emile H. L. Aarts, Wim F. J. Verhaegh, Paul E. R. Lippens
Efficient timing constraint derivation for optimal retiming high speed processing units. HLSS (1994)
Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala
CodeSyn: a retargetable code synthesis system (abstract). HLSS (1994)
Ivan P. Radivojevic, Forrest Brewer
Ensemble representation and techniques for exact control-dependent scheduling. HLSS (1994)
Peter Gutberlet, Wolfgang Rosenstiel
Specification of interface components for synchronous data paths. HLSS (1994)
Proceedings of the 7th International Symposium on High Level Synthesis, HLSS'94, Niagra-on-the-Lake, ON, Canada, May 18-20, 1994 HLSS (1994)
Thomas Charles Wilson, Gary Gréwal, Ben Halley, Dilip K. Banerji
An integrated approach to retargetable code generation. HLSS (1994)