Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator.
Michel R. C. M. BerkelaarPim H. W. BuurmanJochen A. G. JessPublished in: ICCAD (1994)
Keyphrases
- piecewise linear
- power consumption
- trade off
- power dissipation
- low power
- nm technology
- cmos technology
- end to end delay
- energy efficiency
- power management
- power saving
- chaotic map
- dynamic programming
- data center
- energy saving
- battery life
- hyperplane
- principal curves
- smooth curves
- image processing
- high speed
- battery powered
- power reduction