Bart Mesman

Publication Activity (10 Years)

Years Active: 1997-2016
Publications (10 Years): 1

Top Topics

Code Generation

Concave Convex Procedure

Convolutional Neural Networks

Top Venues

Publications

Maurice Peemen, Runbin Shi, Sohan Lal, Ben H. H. Juurlink, Bart Mesman, Henk Corporaal
The neuro vector engine: Flexibility to improve convolutional net efficiency for wearable vision. DATE (2016)
Maurice Peemen, Bart Mesman, Henk Corporaal
Inter-tile reuse optimization applied to bandwidth constrained embedded accelerators. DATE (2015)
Maurice Peemen, Wisnu Pramadi, Bart Mesman, Henk Corporaal
VLIW Code Generation for a Convolutional Network Accelerator. SCOPES (2015)
Maurice Peemen, Arnaud A. A. Setio, Bart Mesman, Henk Corporaal
Memory-centric accelerator design for Convolutional Neural Networks. ICCD (2013)
Dongrui She, Yifan He, Bart Mesman, Henk Corporaal
Scheduling for register file energy minimization in explicit datapath architectures. DATE (2012)
Gert-Jan van den Braak, Cedric Nugteren, Bart Mesman, Henk Corporaal
GPU-Vote: A Framework for Accelerating Voting Algorithms on GPU. Euro-Par (2012)
Maurice Peemen, Bart Mesman, Henk Corporaal
Efficiency Optimization of Trainable Feature Extractors for a Consumer Platform. ACIVS (2011)
Ahsan Shabbir, Sander Stuijk, Akash Kumar, Henk Corporaal, Bart Mesman
An MPSoC design approach for multiple use-cases of throughput constrainted applications. Conf. Computing Frontiers (2011)
Yifan He, Dongrui She, Bart Mesman, Henk Corporaal
MOVE-Pro: A low power and high code density TTA architecture. ICSAMOS (2011)
Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal
Distributed resource management for concurrent execution of multimedia applications on MPSoC platforms. ICSAMOS (2011)
Zhenyu Ye, Yifan He, Roel Pieters, Bart Mesman, Henk Corporaal, Pieter Jonker
Demo: An embedded vision system for high frame rate visual servoing. ICDSC (2011)
Cedric Nugteren, Henk Corporaal, Bart Mesman
Skeleton-based automatic parallelization of image processing algorithms for GPUs. ICSAMOS (2011)
Zhenyu Ye, Yifan He, Roel Pieters, Bart Mesman, Henk Corporaal, Pieter Jonker
Bottlenecks and Tradeoffs in High Frame Rate Visual Servoing: A Case Study. MVA (2011)
Cedric Nugteren, Gert-Jan van den Braak, Henk Corporaal, Bart Mesman
High performance predictable histogramming on GPUs: exploring and evaluating algorithm trade-offs. GPGPU (2011)
Gert-Jan van den Braak, Cedric Nugteren, Bart Mesman, Henk Corporaal
Fast Hough Transform on GPUs: Exploration of Algorithm Trade-Offs. ACIVS (2011)
Yifan He, Zhenyu Ye, Dongrui She, Bart Mesman, Henk Corporaal
Feasibility Analysis of Ultra High Frame Rate Visual Servoing on FPGA and SIMD Processor. ACIVS (2011)
Gert-Jan van den Braak, Bart Mesman, Henk Corporaal
Compile-time GPU memory access optimizations. ICSAMOS (2010)
Ahsan Shabbir, Akash Kumar, Sander Stuijk, Bart Mesman, Henk Corporaal
CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications. J. Syst. Archit. 56 (7) (2010)
Akash Kumar, Bart Mesman, Henk Corporaal, Yajun Ha
Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (4) (2010)
Ahsan Shabbir, Sander Stuijk, Akash Kumar, Bart D. Theelen, Bart Mesman, Henk Corporaal
A predictable communication assist. Conf. Computing Frontiers (2010)
Tim Drijvers, Carlos A. Alba Pinto, Henk Corporaal, Bart Mesman, Gert-Jan van den Braak
Fast Huffman decoding by exploiting data level parallelism. ICSAMOS (2010)
Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal
Performance evaluation of concurrently executing parallel applications on multi-processor systems. ICSAMOS (2009)
Raymond Frijns, Hamed Fatemi, Bart Mesman, Henk Corporaal
DC-SIMD : Dynamic communication for SIMD processors. IPDPS (2008)
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA. ACM Trans. Design Autom. Electr. Syst. 13 (3) (2008)
Akash Kumar, Bart Mesman, Bart D. Theelen, Henk Corporaal, Yajun Ha
Analyzing composability of applications on MPSoC platforms. J. Syst. Archit. 54 (3-4) (2008)
Yifan He, Zoran Zivkovic, Richard P. Kleihorst, Alexander Danilin, Henk Corporaal, Bart Mesman
Real-Time Hough Transform on 1-D SIMD Processors: Implementation and Architecture Exploration. ACIVS (2008)
Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal
Enabling MPSoC Design Space Exploration on FPGAs. IMTIC (2008)
Akash Kumar, Bart Mesman, Henk Corporaal, Bart D. Theelen, Yajun Ha
A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices. DAC (2007)
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal
Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA. FPL (2007)
Akash Kumar, Bart Mesman, Bart D. Theelen, Henk Corporaal, Yajun Ha
Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip. ESTIMedia (2006)
Bart Mesman, Hamed Fatemi, Henk Corporaal, Twan Basten
Dynamic-SIMD for lens distortion compensation. ASAP (2006)
Akash Kumar, Bart Mesman, Henk Corporaal, Jef L. van Meerbergen, Yajun Ha
Global Analysis of Resource Arbitration for MPSoC. DSD (2006)
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Pieter P. Jonker
Run-time reconfiguration of communication in SIMD architectures. IPDPS (2006)
Hamed Fatemi, Bart Mesman, Henk Corporaal, Twan Basten, Richard P. Kleihorst
RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications. J. Embed. Comput. 2 (2) (2006)
Sander Stuijk, Twan Basten, Bart Mesman, Marc Geilen
Predictable embedding of large data structures in multiprocessor networks-on-chip. DSD (2005)
Sander Stuijk, Twan Basten, Bart Mesman, Marc Geilen
Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-Chip. DATE (2005)
Marco Bekooij, Orlando Moreira, Peter Poplavko, Bart Mesman, Milan Pastrnak, Jef L. van Meerbergen
Predictable Embedded Multiprocessor System Design. SCOPES (2004)
Peter Poplavko, Twan Basten, Marco Bekooij, Jef L. van Meerbergen, Bart Mesman
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip. CASES (2003)
Qin Zhao, Bart Mesman, Twan Basten
Static resource models for code-size efficient embedded processors. ACM Trans. Embed. Comput. Syst. 2 (2) (2003)
Bart Mesman, Qin Zhao, Natalino G. Busá, Katarzyna Leijten-Nowak
Reconfigurable Instruction-Set Application-Tuning for DSP. J. Circuits Syst. Comput. 12 (3) (2003)
Qin Zhao, Bart Mesman, Henk Corporaal
Limited Address Range Architecture for Reducing Code Size in Embedded Processors. SCOPES (2003)
Qin Zhao, Bart Mesman, Twan Basten
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models. DATE (2002)
Qin Zhao, Twan Basten, Bart Mesman, C. A. J. van Eijk, Jochen A. G. Jess
Static resource models of instruction sets. ISSS (2001)
Carlos A. Alba Pinto, Bart Mesman, Koen van Eijk, Jochen A. G. Jess
Constraint satisfaction for storage files with Fifos or stacks during scheduling. DATE (2001)
Carlos A. Alba Pinto, Bart Mesman, Jochen A. G. Jess
Constraint Satisfaction for Relative Location Assignment and Scheduling. ICCAD (2001)
Carlos A. Alba Pinto, Koen van Eijk, Bart Mesman, Jochen A. G. Jess
Address Satisfaction for Storage Files with Fifos or Stacks during Scheduling of DSP Algorithms. SBCCI (2000)
Koen van Eijk, Bart Mesman, Carlos A. Alba Pinto, Qin Zhao, Marco Bekooij, Jef L. van Meerbergen, Jochen A. G. Jess
Constraint analysis for code generation: basic techniques and applications in FACTS. ACM Trans. Design Autom. Electr. Syst. 5 (4) (2000)
C. A. J. van Eijk, E. T. A. F. Jacobs, Bart Mesman, Adwin H. Timmer
Identification and Exploitation of Symmetries in DSP Algorithms. DATE (1999)
Bart Mesman, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
Constraint analysis for DSP code generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (1) (1999)
Bart Mesman, Carlos A. Alba Pinto, Koen van Eijk
Efficient Scheduling of DSP Code on Processors with Distributed Register Files. ISSS (1999)
Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
A Constraint Driven Approach to Loop Pipelining and Register Binding. DATE (1998)
Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess
Constraint Analysis for DSP Code Generation. ISSS (1997)