Yajun Ha

ORCID

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 85

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

ISCAS

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Yifei Li, Yuxin Zhou, Yuhao Shu, Hongyu Chen, Yajun Ha
The Optimization of Aging-aware 8T SRAM for FPGA Configuration Memory. ISCAS (2024)
Yi Wang, Yuanjin Zheng, Yajun Ha
Machine Learning with Real-time and Small Footprint Anomaly Detection System for In-Vehicle Gateway. CoRR (2024)
Yi Wang, Yuanjin Zheng, Yajun Ha
Machine Learning with Real-time and Small Footprint Anomaly Detection System for In-Vehicle Gateway. ISCAS (2024)
Xiaoxuan Peng, Xiaohu Ge, Yajun Ha
Modeling and Optimization of XOR Gate Based on Stochastic Thermodynamics. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (1) (2024)
Zhaodong Lv, Hao Sun, Yuhao Shu, Yajun Ha
EarFDA: A Lightweight and Energy-Efficient Fall Detection Accelerator for Ear-Worn Devices. ISCAS (2024)
Weixiong Jiang, Heng Yu, Fupeng Chen, Yajun Ha
AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Hongtu Zhang, Yuhao Shu, Qi Deng, Hao Sun, Wenfeng Zhao, Yajun Ha
WDVR-RAM: A 0.25-1.2 V, 2.6-76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT Workloads. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (10) (2023)
Xinzhe Liu, Jianwen Luo, David Blinder, Fupeng Chen, Heng Yu, Peter Schelkens, Francky Catthoor, Yajun Ha
Data Partition Optimization for High Energy Efficiency by Decoupling Local Dependence in Holographic Video Decoder. ICECS (2023)
Yuhao Shu, Hongtu Zhang, Qi Deng, Hao Sun, Yajun Ha
CIMC: A 603TOPS/W In-Memory-Computing C3T Macro with Boolean/Convolutional Operation for Cryogenic Computing. CICC (2023)
Jianzhong Xiao, Hao Sun, Qi Deng, Xinzhe Liu, Hongtu Zhang, ChengZhang He, Yuhao Shu, Yajun Ha
RPS-KNN: An Ultra-Fast FPGA Accelerator of Range-Projection-Structure K-Nearest-Neighbor Search for LiDAR Odometry in Smart Vehicles. ISCAS (2023)
Rui Li, Heng Yu, Lin Li, Yajun Ha
Criticality-Aware Negotiation-Driven Scrubbing Scheduling for Reliability Maximization in SRAM-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Yuhao Shu, Hongtu Zhang, Hao Sun, Mengru Zhang, Wenfeng Zhao, Qi Deng, Zhidong Tang, Yumeng Yuan, Yongqi Hu, Yu Gu, Xufeng Kou, Yajun Ha
Cryogenic quasi-static embedded DRAM for energy-efficient compute-in-memory applications. CoRR (2023)
Yajun Ha
Outgoing Editorial. IEEE Trans. Circuits Syst. II Express Briefs 70 (12) (2023)
Guangyao Yan, Xinzhe Liu, Hui Wang, Yajun Ha
Fast FPGA Accelerator of Graph Cut Algorithm with Out-of-order Parallel Execution in Folding Grid Architecture. DAC (2023)
Yuhao Shu, Hongtu Zhang, Hao Sun, Qi Deng, Yajun Ha
CSDB-eDRAM: A 16Kb Energy-Efficient 4T CSDB Gain Cell eDRAM with over 16.6s Retention Time and 49.23uW/Kb at 4.2K for Cryogenic Computing. ISCAS (2023)
Qixing Zhang, Hao Sun, Qi Deng, Heng Yu, Yajun Ha
NORB: A Stream-Based and Non-Blocking FPGA Accelerator for ORB Feature Extraction. ICECS (2023)
Yunhao Hu, Hao Sun, Chunxu Guo, Qi Deng, Yajun Ha
An Energy-efficient and Fast KNN Search Accelerator for Large Scale Point Cloud Map. ICECS (2023)
Weixiong Jiang, Heng Yu, Yajun Ha
A High-Throughput Full-Dataflow MobileNetv2 Accelerator on Edge FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (5) (2023)
Lin Li, Rui Li, Yajun Ha
A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Yifei Li, Jian Chen, Yuqi Wang, Zihan Yin, Hongyu Chen, Yajun Ha
A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path. CICC (2023)
Hao Sun, Qi Deng, Xinzhe Liu, Yuhao Shu, Yajun Ha
An Energy-Efficient Stream-Based FPGA Implementation of Feature Extraction Algorithm for LiDAR Point Clouds With Effective Local-Search. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (1) (2023)
Yuqi Wang, Shen Zhang, Yifei Li, Jian Chen, Wenfeng Zhao, Yajun Ha
Assist and Bitline Leakage Compensation. IEEE Trans. Very Large Scale Integr. Syst. 31 (5) (2023)
Jianwen Luo, Xinzhe Liu, Fupeng Chen, Yajun Ha
HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (11) (2023)
Fupeng Chen, Heng Yu, Weixiong Jiang, Yajun Ha
Quality Optimization of Adaptive Applications via Deep Reinforcement Learning in Energy Harvesting Edge Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Jian Chen, Wenfeng Zhao, Yuqi Wang, Yuhao Shu, Weixiong Jiang, Yajun Ha
A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations. IEEE Trans. Very Large Scale Integr. Syst. 30 (6) (2022)
Shaoyi Chen, Zhiqi Zhou, Yajun Ha
An Ultra Energy Efficient Streaming-based FPGA Accelerator for Lightweight Neural Network. ISCAS (2022)
Guangyao Yan, Xinzhe Liu, Fupeng Chen, Hui Wang, Yajun Ha
Ultra-Fast FPGA Implementation of Graph Cut Algorithm With Ripple Push and Early Termination. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (4) (2022)
Yunxiang Zhang, Biao Sun, Weixiong Jiang, Yajun Ha, Miao Hu, Wenfeng Zhao
WSQ-AdderNet: Efficient Weight Standardization Based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization. ICCAD (2022)
Yajun Ha
Incoming Editorial. IEEE Trans. Circuits Syst. II Express Briefs 69 (1) (2022)
Weixiong Jiang, Heng Yu, Hongtu Zhang, Yuhao Shu, Rui Li, Jian Chen, Yajun Ha
FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA. IEEE Trans. Very Large Scale Integr. Syst. 30 (4) (2022)
Chunxu Guo, Yi Wang, Fupeng Chen, Yajun Ha
Unified Lightweight Authenticated Encryption for Resource-Constrained Electronic Control Unit. ICECS 2022 (2022)
Zhengpeng Liao, Deyang Jiang, Xiaochun Liu, Andreas Velten, Yajun Ha, Xin Lou
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (2) (2022)
Jianwen Luo, Xinzhe Liu, Fupeng Chen, Yajun Ha
Hierarchical and Recursive Floorplanning Algorithm for NoC-Bascd Scalable Multi-Die FPGAs. APCCAS (2022)
Yi Wang, Marc Stöttinger, Yajun Ha
A Fault Resistant AES via Input-Output Differential Tables with DPA Awareness. ISCAS (2021)
Zhenpeng He, Hao Sun, Jiawei Hou, Yajun Ha, Sören Schwertfeger
Hierarchical topometric representation of 3D robotic maps. Auton. Robots 45 (5) (2021)
Yajun Ha, Edoardo Bonizzoni
Guest Editorial Special Issue on the 2021 IEEE International Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. II Express Briefs 68 (5) (2021)
Jian Chen, Wenfeng Zhao, Yuqi Wang, Yajun Ha
Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (4) (2021)
Qi Deng, Hao Sun, Fupeng Chen, Yuhao Shu, Hui Wang, Yajun Ha
An Optimized FPGA-Based Real-Time NDT for 3D-LiDAR Localization in Smart Vehicles. IEEE Trans. Circuits Syst. II Express Briefs 68 (9) (2021)
Xinzhe Liu, Fupeng Chen, Raees Kizhakkumkara Muhamad, David Blinder, Dessislava Nikolova, Peter Schelkens, Francky Catthoor, Yajun Ha
Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation. DAC (2021)
Hongtu Zhang, Yuhao Shu, Weixiong Jiang, Zihan Yin, Wenfeng Zhao, Yajun Ha
A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 68 (5) (2021)
Fupeng Chen, Xinzhe Liu, Heng Yu, Yajun Ha
CLIF: Cross-Layer Information Fusion for Stereo Matching and its Hardware Implementation. ISCAS (2021)
Weixiong Jiang, Heng Yu, Xinzhe Liu, Hao Sun, Rui Li, Yajun Ha
TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer. DAC (2021)
Yajun Ha, Edoardo Bonizzoni
Guest Editorial Special Issue on the 2021 ISICAS: A CAS Journal Track Symposium. IEEE Trans. Circuits Syst. II Express Briefs 68 (9) (2021)
Zhenpeng He, Hao Sun, Jiawei Hou, Yajun Ha, Sören Schwertfeger
Hierarchical Topometric Representation of 3D Robotic Maps. CoRR (2021)
Jian Chen, Wenfeng Zhao, Yuqi Wang, Yajun Ha
Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access. IEEE Trans. Circuits Syst. II Express Briefs 68 (12) (2021)
Heng Yu, Yajun Ha, Bharadwaj Veeravalli, Fupeng Chen, Hesham El-Sayed
DVFS-Based Quality Maximization for Adaptive Applications With Diminishing Return. IEEE Trans. Computers 70 (5) (2021)
Yi Wang, Dan Wei Ming Chia, Yajun Ha
Vulnerability of Deep Learning Model based Anomaly Detection in Vehicle Network. MWSCAS (2020)
Yuqi Wang, Jian Chen, Yu Pu, Yajun Ha
Energy-Efficient Arbitrary Precision Multi-Bit Multiplication with Bi-Serial In/Near Memory Computing. ISCAS (2020)
Weixiong Jiang, Rui Li, Heng Yu, Yajun Ha
An Accurate FPGA Online Delay Monitor Supporting All Timing Paths. ISCAS (2020)
Yajun Ha, Edoardo Bonizzoni
Guest Editorial Special Issue on the 2020 IEEE International Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. II Express Briefs (5) (2020)
Yajun Ha, Edoardo Bonizzoni
Guest Editorial Special Issue on the 2020 ISICAS: A CAS Journal Track Symposium. IEEE Trans. Circuits Syst. II Express Briefs (9) (2020)
Rui Li, Heng Yu, Weixiong Jiang, Yajun Ha
DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs. DAC (2020)
Ruiqi Luo, Xiaolei Chen, Yajun Ha
Optimization of FPGA Routing Networks with Time-Multiplexed Interconnects. LASCAS (2020)
Hongxi Dong, Manzhen Wang, Yuanyong Luo, Muhan Zheng, Mengyu An, Yajun Ha, Hongbing Pan
PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions. IEEE Trans. Very Large Scale Integr. Syst. 28 (9) (2020)
Hao Sun, Xinzhe Liu, Qi Deng, Weixiong Jiang, Shaobo Luo, Yajun Ha
Efficient FPGA Implementation of K-Nearest-Neighbor Search Algorithm for 3D LIDAR Localization and Mapping in Smart Vehicles. IEEE Trans. Circuits Syst. II Express Briefs (9) (2020)
Huaqing Sun, Yuanyong Luo, Yajun Ha, Yinghuan Shi, Yang Gao, Qinghong Shen, Hongbing Pan
A Universal Method of Linear Approximation With Controllable Error for the Efficient Implementation of Transcendental Functions. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2020)
Fupeng Chen, Heng Yu, Yajun Ha
Quality Estimation and Optimization of Adaptive Stereo Matching Algorithms for Smart Vehicles. ACM Trans. Embed. Comput. Syst. 19 (2) (2020)
Jian Chen, Wenfeng Zhao, Yajun Ha
Area-Efficient Distributed Arithmetic Optimization via Heuristic Decomposition and In-Memroy Computing. ASICON (2019)
Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan
Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base". IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Wenfeng Zhao, Biao Sun, Jian Chen, Yajun Ha
AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design. SoCC (2019)
Weixiong Jiang, Heng Yu, Xinzhe Liu, Yajun Ha
Energy Efficiency Optimization of FPGA-based CNN Accelerators with Full Data Reuse and VFS. ICECS (2019)
Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan
Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Weixiong Jiang, Heng Yu, Yajun Ha
Enabling Fine-Grained Dynamic Voltage and Frequency Scaling in SDSoC. SoCC (2019)
Xinzhe Liu, Fupeng Chen, Yajun Ha
Area Efficient Box Filter Acceleration by Parallelizing with Optimized Adder Tree. ISVLSI (2019)
Tian Huang, Yongxin Zhu, Yajun Ha, Xu Wang, Meikang Qiu
A Hardware Pipeline with High Energy and Resource Efficiency for FMM Acceleration. ACM Trans. Embed. Comput. Syst. 17 (2) (2018)
Yun Liang, Shuo Wang, Tulika Mitra, Yajun Ha
Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical Applications. ACA (2018)
Xu Wang, Yongxin Zhu, Yajun Ha, Meikang Qiu, Tian Huang
An FPGA-Based Cloud System for Massive ECG Data Analysis. IEEE Trans. Circuits Syst. II Express Briefs (3) (2017)
Yi Wang, Yajun Ha
A DFA-Resistant and Masked PRESENT with Area Optimization for RFID Applications. ACM Trans. Embed. Comput. Syst. 16 (4) (2017)
Heng Yu, Yajun Ha, Jing Wang
Quality Optimization of Resilient Applications under Temperature Constraints. Conf. Computing Frontiers (2017)
Xu Wang, Yongxin Zhu, Yajun Ha, Meikang Qiu, Tian Huang, Xueming Si, Jiangxing Wu
An energy-efficient system on a programmable chip platform for cloud applications. J. Syst. Archit. 76 (2017)
Wenfeng Zhao, Ang Li, Yi Wang, Yajun Ha
Analysis and design of energy-efficient data-dependent SRAM. ASICON (2017)
Chin Hau Hoo, Yajun Ha, Akash Kumar
ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning. FPL (2016)
Yi Wang, Jianfeng An, Yajun Ha
Unified data authenticated encryption for vehicular communication. MWSCAS (2016)
Yi Wang, Yajun Ha
High throughput and resource efficient AES encryption/decryption for SANs. ISCAS (2016)
Mengyao Zhu, Yajun Ha, Chengcun Gu, Liuchuang Gao
An Optimized Logarithmic Converter With Equal Distribution of Relative Errors. IEEE Trans. Circuits Syst. II Express Briefs (9) (2016)
Tian Huang, Yongxin Zhu, Yishu Mao, Xinyang Li, Mengyun Liu, Yafei Wu, Yajun Ha, Gillian Dobbie
Parallel Discord Discovery. PAKDD (2) (2016)
Thi Hanh Nguyen, Yi Wang, Yajun Ha, Renfa Li
Performance and security-enhanced fuzzy vault scheme based on ridge features for distorted fingerprints. IET Biom. 4 (1) (2015)
Wenfeng Zhao, Anastacia B. Alvarez, Yajun Ha
A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter With Wide Conversion Range. IEEE Trans. Circuits Syst. II Express Briefs (7) (2015)
Wenfeng Zhao, Yajun Ha, Massimo Alioto
AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. ISCAS (2015)
Chin Hau Hoo, Akash Kumar, Yajun Ha
ParaLaR: A parallel FPGA router based on Lagrangian relaxation. FPL (2015)
Wenfeng Zhao, Yajun Ha, Massimo Alioto
Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study. IEEE Trans. Very Large Scale Integr. Syst. 23 (8) (2015)
Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo
TRISHUL: A Single-pass Optimal Two-level Inclusive Data Cache Hierarchy Selection Process for Real-time MPSoCs. CoRR (2015)
Yi Wang, Zhiqian Hong, Jun Li, Shaobo Luo, Yajun Ha
Challenges and future trends for embedded security in electric vehicular communications. ASICON (2015)
Ang Li, Akash Kumar, Yajun Ha, Henk Corporaal
Correlation ratio based volume image registration on GPUs. Microprocess. Microsystems 39 (8) (2015)
Guiyuan Jiang, Jigang Wu, Yajun Ha, Yi Wang, Jizhou Sun
Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms. IEEE Trans. Computers 64 (10) (2015)
Heng Yu, Rizwan Syed, Yajun Ha
Thermal-aware frequency scaling for adaptive workloads on heterogeneous MPSoCs. DATE (2014)
Yi Wang, Yajun Ha
A Performance and Area Efficient ASIP for Higher-Order DPA-Resistant AES. IEEE J. Emerg. Sel. Topics Circuits Syst. 4 (2) (2014)
Kejie Huang, Yajun Ha, Rong Zhao, Akash Kumar, Yong Lian
A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2014)
Qiang Wu, Yajun Ha, Akash Kumar, Shaobo Luo, Ang Li, Shihab Mohamed
A heterogeneous platform with GPU and FPGA for power efficient high performance computing. ISIC (2014)
Yi Wang, Akash Kumar, Yajun Ha
FPGA-based high throughput XTS-AES encryption/decryption for storage area network. FPT (2014)
Wenfeng Zhao, Rui Pan, Yajun Ha, Zhi Yang
A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor. A-SSCC (2014)
Yongzhen Chen, Miguel Rodel Felipe, Yi Wang, Yajun Ha, Shu Qin Ren, Khin Mi Mi Aung
sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface. FPT (2013)
Chin Hau Hoo, Yajun Ha, Akash Kumar
A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm. FPL (2013)
Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, Anastacia B. Alvarez
Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology. ISLPED (2013)
Junsong Hou, Heng Yu, Yajun Ha, Xin Liu
The architecture and placement algorithm for a uni-directional routing based 3D FPGA. FPT (2013)
Heng Yu, Bharadwaj Veeravalli, Yajun Ha, Shaobo Luo
Dynamic Scheduling of Imprecise-Computation Tasks on Real-Time Embedded Multiprocessors. CSE (2013)
Wei Ting Loke, Wenfeng Zhao, Yajun Ha
Criticality-based routing for FPGAS with reverse body bias switch box architectures. FPL (2013)
Yi Wang, Yajun Ha
FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network. IEEE Trans. Circuits Syst. II Express Briefs (1) (2013)
Heng Yu, Yajun Ha, Bharadwaj Veeravalli
Quality-Driven Dynamic Scheduling for Real-Time Adaptive Applications on Multiprocessor Systems. IEEE Trans. Computers 62 (10) (2013)
Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo
TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs. ASP-DAC (2013)

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Publication Activity (10 Years)

Top Topics

Top Venues

Yajun Ha