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Chin Hau Hoo
Publication Activity (10 Years)
Years Active: 2012-2018
Publications (10 Years): 4
Top Topics
Fine Grain
Shared Memory
Parallel Processing
Lagrangian Relaxation
Top Venues
FPL
FCCM
ISLPED
FPGA
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Publications
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Chin Hau Hoo
,
Akash Kumar
ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling.
FPGA
(2018)
Chin Hau Hoo
,
Akash Kumar
ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding.
FCCM
(2017)
Chin Hau Hoo
,
Yajun Ha
,
Akash Kumar
ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning.
FPL
(2016)
Chin Hau Hoo
,
Akash Kumar
,
Yajun Ha
ParaLaR: A parallel FPGA router based on Lagrangian relaxation.
FPL
(2015)
Chin Hau Hoo
,
Yajun Ha
,
Akash Kumar
A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm.
FPL
(2013)
Wenfeng Zhao
,
Yajun Ha
,
Chin Hau Hoo
,
Anastacia B. Alvarez
Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology.
ISLPED
(2013)
Chin Hau Hoo
,
Akash Kumar
An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay.
FPL
(2012)