Anastacia B. Alvarez

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 26

Top Topics

Wireless Sensor

Hamming Distance

Random Number Generator

Top Venues

Publications

Lawrence Roman A. Quizon, Anastacia B. Alvarez
Federated Learning with MLPerfTiny Tasks and Server-side Momentum. ICMLSC (2024)
Fredrick Angelo R. Galapon, Anastacia B. Alvarez
A Hyperdimensional Computing Architecture with 4.4x Energy Efficiency in 65nm CMOS. ISCAS (2024)
Kim Isaac I. Buelagala, Ginzy S. Javier, Sean Alfred A. Lipardo, James Carlo E. Sorsona, Sherry Joy Alvionne S. Baquiran, Lawrence Roman A. Quizon, Allen Jason A. Tan, Ryan Albert G. Antonio, Fredrick Angelo R. Galapon, Anastacia B. Alvarez
Energy-Efficient Sparse Hyperdimensional Computing for Speech Recognition. ISOCC (2023)
Giussepe Yvanric Galvez, Andrew James Lim, Christopher Jr Camarillo, John Rey Marturillas, Mark Emannuel Teodoro, Ellris Kristian Nuel Urfano, Anastacia B. Alvarez, Ryan Albert G. Antonio, Fredrick Angelo R. Galapon, Sherry Joy Alvionne Baquiran, Allen Jason Tan, Lawrence Roman A. Quizon
Integration of In-Memory Computing Capabilities to a Self-Matching Complementary-Reference Sensing Scheme for TST-MRAM. ISOCC (2023)
Ryan Albert G. Antonio, Anastacia B. Alvarez
Redundancy Pruning for Binary Hyperdimensional Computing Architectures. ISCAS (2022)
Lawrence Roman A. Quizon, Anastacia B. Alvarez, Christoper G. Santos, Marc D. Rosales, John Richard E. Hizon, Maria Patricia Rouelli G. Sabino
A Voltage-Controlled Magnetic Anisotropy based True Random Number Generator. ISOCC (2021)
Ryan Albert G. Antonio, Anastacia B. Alvarez
Bit-Selection Control for Energy-Efficient Handwritten Digits Recognition Hyperdimensional Computing Architecture. TENCON (2020)
Michael Joseph Neri, Redentor Immanuel Ridao, Victor Emmanuel Baylosis, Phoebe Meira Chua, Allen Jason Tan, Maria Theresa G. de Leon, John Richard E. Hizon, Marc D. Rosales, Maria Patricia Rouelli Sabino-Santos, Christopher Santos, Anastacia B. Alvarez
Design and Implementation of a Pipelined RV32IMC Processor with Interrupt Support for Large-Scale Wireless Sensor Networks. TENCON (2020)
Arriel Ting, Anastacia B. Alvarez, Maria Theresa G. de Leon, Marc D. Rosales, Maria Patricia Rouelli Sabino-Santos, John Richard E. Hizon, Christopher Santos
Designing a Class E Power Amplifier through Modeling in Verilog-A. ISOCC (2020)
Ian Christian Fernandez, Maria Theresa G. de Leon, Anastacia B. Alvarez, Marc D. Rosales
An Energy-Efficient Temperature Sensor Using CMOS Thyristor Delay Elements. ICM (2020)
Anastacia B. Alvarez, Gopalakrishnan Ponnusamy, Massimo Alioto
Energy-Quality Scalable Memory-Frugal Feature Extraction for Always-On Deep Sub-mW Distributed Vision. IEEE Access 8 (2020)
Maverick Jonas G. Adonis, Renzo S. Forteza, Alaine Richelle C. Ramos, Anastacia B. Alvarez, Maria Theresa G. de Leon, John Richard E. Hizon, Maria Patricia Rouelli Sabino-Santos, Christopher G. Santos, Marc D. Rosales
FPGA-based Features Extraction Sensor for Lettuce Crop. TENCON (2020)
Christian Joseph Dia, Ralfael Himor, Anastacia B. Alvarez, John Richard E. Hizon, Marc D. Rosales, Maria Patricia Rouelli Sabino-Santos, Christopher Santos, Maria Theresa G. de Leon
An Interface for Shock Inputs in Piezoelectric Energy Harvesting using Synchronous Electric Charge Extraction. ISOCC (2020)
Sean Kane Lloyd M. Quintans, Francesca Bea V. Narcida, Janelle Eira A. Tordesillas, Maria Patricia Rouelli G. Sabino, Anastacia B. Alvarez, Maria Theresa G. de Leon, John Richard E. Hizon, Christopher G. Santos, Marc D. Rosales
5 Gb/s Optical Transceiver for MEMS Tunable HCG-VCSEL in 65 nm CMOS. ISOCC (2020)
Fredrick Angelo R. Galapon, Mark Allen D. C. Agaton, Arcel G. Leynes, Lemuel Neil M. Noveno, Anastacia B. Alvarez, Chris Vincent J. Densing, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon, Rico Jossel M. Maestro
A 0.5 V Low-Power All-Digital Phase-Locked Loop in 65 nm Complementary Metal-Oxide-Semiconductor Process. J. Low Power Electron. 15 (1) (2019)
Phoebe Laine Panis, Maria Sophia Ralota, Joenard Matanguihan, Anastacia B. Alvarez, John Richard E. Hizon, Marc D. Rosales, Christopher Santos, Maria Theresa G. de Leon
Design and Implementation a Self-starting Thermal Energy Harvester with Resonant Startup and Maximum Power Point Tracking Capabilities/or Wireless Sensor Nodes. ISOCC (2019)
Gio Ishmael Evidente, Steven Lorenzo Mindoro, Anastacia B. Alvarez, Chris Vincent J. Densing, Rico Jossel M. Maestro, Marc D. Rosales, Maria Theresa G. de Leon
An Ultra-Low Power Direct Active-RF Detection Wake-Up Receiver with Noise-Cancelling Envelope Detector in 65 nm CMOS Process. TENCON (2018)
Fredrick Angelo R. Galapon, Mark Allen D. C. Agaton, Arcel G. Leynes, Lemuel Neil M. Noveno, Anastacia B. Alvarez, Chris Vincent J. Densing, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon, Rico Jossel M. Maestro
Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process. NGCAS (2018)
Uziel Rein Agub, Jhake Zebedee Aquino, Justine Beano, Rommel Monsayac, Anastacia B. Alvarez, Maria Theresa G. de Leon, Chris Vincent J. Densing, John Richard E. Hizon, Rico Jossel M. Maestro, Marc D. Rosales
A Study on Coarse Stage Bit Allocation to Improve Power Efficiency of a 10-bit Coarse-Fine SAR ADC Implemented in 65nm CMOS Process for Environmental Sensing Applications. TENCON (2018)
Zyrel Renzo Sanchez, Sam Jason Vasquez, Anastacia B. Alvarez, Chris Vincent J. Densing, John Richard E. Hizon, Rico Jossel M. Maestro, Maria Theresa G. de Leon, Marc D. Rosales
A gm/ID Based Algorithm for the Design of CMOS Miller Operational Amplifiers in 65 nm Technology. TENCON (2018)
Sachin Taneja, Anastacia B. Alvarez, Massimo Alioto
Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm. IEEE J. Solid State Circuits 53 (10) (2018)
Fredrick Angelo R. Galapon, Mark Allen D. C. Agaton, Arcel G. Leynes, Lemuel Neil M. Noveno, Anastacia B. Alvarez, Chris Vincent J. Densing, John Richard E. Hizon, Marc D. Rosales, Maria Theresa G. de Leon, Rico Jossel M. Maestro
A 0.5V Low-Power All-Digital Phase-Locked Loop in 65nm CMOS Process for Wireless Sensing Applications. TENCON (2018)
George Procyon Cabrera, Jhelsea Credo, Gio Ishmael Evidente, Ralen Rose Gloria Malatbalat, Steven Lorenzo Mindoro, Arlo Ricardo Sanico, Anastacia B. Alvarez, Chris Vincent J. Densing, Rico Jossel M. Maestro, Marc D. Rosales, Maria Theresa G. de Leon
A 2.4 GHz Energy-efficient Short-range Receiver with Wake-up and Multiple Gain Settings for Wireless Sensor Networks. TENCON (2018)
Anastacia B. Alvarez, Gopalakrishnan Ponnusamy, Massimo Alioto
area in 40nm CMOS. A-SSCC (2017)
Sachin Taneja, Anastacia B. Alvarez, Gopalakrishnan Sadagopan, Massimo Alioto
A fully-synthesizable C-element based PUF featuring temperature variation compensation with native 2.8% BER, 1.02fJ/b at 0.8-1.0V in 40nm. A-SSCC (2017)
Anastacia B. Alvarez, Wenfeng Zhao, Massimo Alioto
Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm. IEEE J. Solid State Circuits 51 (3) (2016)
Anastacia B. Alvarez, Wenfeng Zhao, Massimo Alioto
14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm. ISSCC (2015)
Wenfeng Zhao, Anastacia B. Alvarez, Yajun Ha
A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter With Wide Conversion Range. IEEE Trans. Circuits Syst. II Express Briefs (7) (2015)
Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, Anastacia B. Alvarez
Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology. ISLPED (2013)
Christiensen D. C. Arandilla, Anastacia B. Alvarez, Christian Raymund K. Roque
Static Noise Margin of 6T SRAM Cell in 90-nm CMOS. UKSim (2011)
Jestoni V. Zarsuela, Anastacia B. Alvarez, Joy Alinda Reyes
A Simulation of Cache Sub-banking and Block Buffering as Power Reduction Techniques for Multiprocessor Cache Design. UKSim (2010)
Rosario M. Reas, Anastacia B. Alvarez, Joy Alinda P. Reyes
Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL. UKSim (2010)