A 0.5V Low-Power All-Digital Phase-Locked Loop in 65nm CMOS Process for Wireless Sensing Applications.
Fredrick Angelo R. GalaponMark Allen D. C. AgatonArcel G. LeynesLemuel Neil M. NovenoAnastacia B. AlvarezChris Vincent J. DensingJohn Richard E. HizonMarc D. RosalesMaria Theresa G. de LeonRico Jossel M. MaestroPublished in: TENCON (2018)
Keyphrases
- low power
- phase locked loop
- wireless transmission
- cmos technology
- power consumption
- ultra low power
- mixed signal
- low cost
- high speed
- image sensor
- nm technology
- high voltage
- multipath
- single chip
- digital signal processing
- power reduction
- high power
- real time
- wireless networks
- vlsi circuits
- logic circuits
- vlsi architecture
- low power consumption
- wireless communication
- sensor networks
- wifi
- delay insensitive
- mobile ad hoc networks
- cognitive radio
- wireless channels
- hardware implementation
- end to end
- cmos image sensor
- high frequency