Static Noise Margin of 6T SRAM Cell in 90-nm CMOS.
Christiensen D. C. ArandillaAnastacia B. AlvarezChristian Raymund K. RoquePublished in: UKSim (2011)
Keyphrases
- power consumption
- cmos technology
- low power
- nm technology
- random access memory
- low voltage
- high speed
- random noise
- low cost
- noise level
- silicon on insulator
- noisy data
- power reduction
- design considerations
- objective function
- noise model
- support vector
- single chip
- image sensor
- high frequency
- analog vlsi
- vlsi circuits
- training set