Power Optimization of a 0.5V 0.286-to-18MHz ADPLL in 65nm CMOS Process.
Fredrick Angelo R. GalaponMark Allen D. C. AgatonArcel G. LeynesLemuel Neil M. NovenoAnastacia B. AlvarezChris Vincent J. DensingJohn Richard E. HizonMarc D. RosalesMaria Theresa G. de LeonRico Jossel M. MaestroPublished in: NGCAS (2018)
Keyphrases
- user friendly
- optimization algorithm
- optimization process
- optimization problems
- power losses
- cmos technology
- global optimization
- optimization method
- power transmission
- optimization methods
- power consumption
- high speed
- combinatorial optimization
- real time
- simulated annealing
- multiresolution
- evolutionary algorithm
- data sets