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WSQ-AdderNet: Efficient Weight Standardization Based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization.
Yunxiang Zhang
Biao Sun
Weixiong Jiang
Yajun Ha
Miao Hu
Wenfeng Zhao
Published in:
ICCAD (2022)
Keyphrases
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high density
verilog hdl
optimal design
low density
real time image processing
field programmable gate array
digital signal processing
signal processing
database
hardware design
magnetic recording
design process
single chip
high bandwidth
high speed
state space
databases