Yongzhen Chen

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 48

Top Topics

Feature Matching

Calibration Method

Fish Eye Lenses

Cepstral Coefficients

Top Venues

Publications

Huajun Yao, Yangxin Xiang, Yongzhen Chen, Jiangfeng Wu
A Foreground Wide-Band Receiver I/Q Mismatch Calibration Method in FDD Transceiver. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (6) (2024)
Junkun Chen, Youzhi Gu, Miaomiao Xu, Yongzhen Chen, Cuixia Wang, Jiangfeng Wu
A 4.75-64 Gb/s PAM-4 Wireline Transmitter with 3-tap FFE in 28-nm CMOS. ISCAS (2023)
Weibo Li, Minghao Jiang, Yongzhen Chen, Jiangfeng Wu
Complexity-Reduced Joint Calibration for Nonlinearity and I/Q Imbalance in Direct-Conversion Transmitters. ASICON (2023)
Xinhao Xu, Yongzhen Chen, Jiangfeng Wu
A low-power daisy-chain controller implemention in BMS based on power mode switching. ASICON (2023)
Jiangshan Zhao, Jiankun Huang, Yongzhen Chen, Jiangfeng Wu
A Low-power Digital Automatic Gain Control Design in Wireless Communication Receivers. ASICON (2023)
Xiaoping Xie, Yongzhen Chen, Rufeng Shen, Dan Tian
Research on monaural speech segregation based on feature selection. EURASIP J. Audio Speech Music. Process. 2023 (1) (2023)
Yiwei Zhou, Weibo Li, Yongzhen Chen
Nonlinear modeling of MIMO antenna array power amplifiers based on time-delay neural network. ASICON (2023)
Huajun Yao, Yangxin Xiang, Yongzhen Chen, Cuixia Wang, Jiangfeng Wu
A Wideband Receiver I/Q Mismatch Calibration Method in FDD Transceiver. ISCAS (2023)
Hang Ling, Yifei Bai, Fengyi Mei, Huajun Yao, Yongzhen Chen, Jiangfeng Wu
Pipelined-SAR ADC Calibration Technique Based on Gain-Bit Weights. ASICON (2023)
Jun Chen, Fengyi Mei, Mingzhe Liu, Yongzhen Chen, Jiangfeng Wu
A 32GS/s 7bit TI-SAR ADC in 28nm for 32Gb/s ADC-Based SerDes Receiver. ASICON (2023)
Jie Ding, Yongzhen Chen, Cuixia Wang, Jiangfeng Wu
A Foreground LSB-Based Capacitor Mismatch Calibration Method in An 18-bit SAR ADC. ISCAS (2023)
Jingchao Lan, Danfeng Zhai, Yongzhen Chen, Zhekan Ni, Xingchen Shen, Fan Ye, Junyan Ren
A 2.5-GS/s Time-Interleaved SAR-Assisted Ringamp-Based Pipelined ADC with Digital Background Calibration. ISCAS (2022)
Minghao Jiang, Chenyang Han, Weibo Li, Jiangfeng Wu, Yongzhen Chen
0.7-6 GHz Programable Gain Push-Pull Driver PA Based on Dual-Loop Biases. APCCAS (2022)
Yangxin Xiang, Chenyang Han, Cuixia Wang, Jiangfeng Wu, Yongzhen Chen
A Current-Mode, 30 dB Range with 0.5 dB Step, 0.1 to 6 GHz Attenuator for Wideband Receiver. MWSCAS (2022)
Xinjie Feng, Yongzhen Chen, Youzhi Gu, Jiangfeng Wu
A 64Gb/s PAM-4 Digital Equalizer With Tap-Configurable FFE and Partially Unrolled DFE in 28nm CMOS. ICTA (2022)
Xinghui Zhu, Yongzhen Chen, Xiaodong Zhang, Zhiwei Zhang, Baoquan Ren
Feature Matching for Indoor-Oriented Visual Odometry. NaNA (2022)
Jingchao Lan, Yongzhen Chen, Xingchen Shen, Zhekan Ni, Yimin Wu, Fan Ye, Junyan Ren
Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation. IEEE Trans. Circuits Syst. II Express Briefs 69 (2) (2022)
Liran Dong, Yujun Shu, Yongzhen Chen, Jiangfeng Wu
A 2-GS/s 200-MHz BW Oversampling Continuous-Time Pipeline ADC with Adaptive Digital Filter in 28nm. ICTA (2021)
Jiankun Huang, Xinjie Feng, Congying Zhou, Yongzhen Chen
A High-Performance Mel-scale Frequency Cepstral Coefficients Digital Circuit Used on Keyword-Spotting Chip. ASICON (2021)
Yujie Wu, Gang Zhang, Yongzhen Chen, Jiangfeng Wu
A 6-bit Active Phase Shifter with Quadrature Outputs. ASICON (2021)
Li Zhang, Yunchuan Wang, Fengyi Mei, Yongzhen Chen, Jiangfeng Wu
An Input Buffer for 4 GS/s 14-b Time-Interleaved ADC. ASICON (2021)
Yunchuan Wang, Li Zhang, Fengyi Mei, Yongzhen Chen, Jiangfeng Wu
Digital Calibration of Capacitor Mismatch and Gain Error in Pipelined SAR ADCs. ASICON (2021)
Runze Chi, Junkun Chen, Youzhi Gu, Jiangfeng Wu, Yongzhen Chen
A 161mW 32Gb/s ADC-Based NRZ SerDes Receiver Front End in 28nm. ICTA (2021)
Yuefeng Cao, Shumin Zhang, Tianli Zhang, Yongzhen Chen, Yutong Zhao, Chixiao Chen, Fan Ye, Junyan Ren
A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (2) (2021)
Youzhi Gu, Junkun Chen, Xiaolin Li, Yongzhen Chen, Jiangfeng Wu
A 32Gb/s NRZ Wireline Transmitter with CMFB- Based CML Driver in 28nm CMOS Technology. MWSCAS (2021)
Yangxin Xiang, Saisai Jin, Yongzhen Chen, Jiangfeng Wu
A 71dB DC Gain, 0.1% THD, 0.5-V Bulk-Driven Class-AB OTA Achieved by Novel CMFB Methods. MWSCAS (2021)
Xiaozhe Wang, Lingzhi Su, Xiyuan Du, Yongzhen Chen, Jiangfeng Wu
Physical Coding Sublayer For 32Gbps SerDes Based On JESD204C. ASICON (2021)
Yongzhen Chen, Xingchen Shen, Zhekan Ni, Jingchao Lan, Chixiao Chen, Fan Ye, Junyan Ren
A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps. ESSCIRC (2019)
Qi Li, Yujun Shu, Yongzhen Chen, Jiangfeng Wu
An Area-Efficient Multi-Rate Digital Decimator. ASICON (2019)
Zhekan Ni, Yongzhen Chen, Fan Ye, Junyan Ren
A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. Microelectron. J. 84 (2019)
Pingshun Ma, Yongzhen Chen, Jiangfeng Wu
A Double-Latch Comparator for Multi-GS/s SAR ADCs in 28nm CMOS. ASICON (2019)
Yongzhen Chen, Jiangfeng Wu
High Linear Ring Amplifier Design with Analysis on Settling Procedures. ASICON (2019)
Yongzhen Chen, Jingjing Wang, Hang Hu, Fan Ye, Junyan Ren
A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier. IEEE Trans. Circuits Syst. II Express Briefs (11) (2018)
Yuefeng Cao, Tianli Zhang, Yongzhen Chen, Fan Ye, Junyan Ren
An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs. ISCAS (2018)
Yuefeng Cao, Yongzhen Chen, Zhekan Ni, Fan Ye, Junyan Ren
An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC. APCCAS (2018)
Yongzhen Chen, Fan Ye, Junyan Ren
An 8.2 fJ/conversion-step 9-bit 135 MS/s SAR ADC with redundant methods for acceleration. Microelectron. J. 73 (2018)
Manxin Li, Yongzhen Chen, Fan Ye, Junyan Ren
A 100MS/S 12-bit Coarse-Fine SAR ADC with Shared Split-CDAC. ISCAS (2018)
Zhekan Ni, Yongzhen Chen, Fan Ye, Junyan Ren
A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic. APCCAS (2018)
Yongzhen Chen, Zhekan Ni, Yuefeng Cao, Fan Ye, Junyan Ren
A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation. ISCAS (2018)
Zhiyuan Dai, Hang Hu, Yongzhen Chen, Fan Ye, Junyan Ren
A 12-Bit ENOB 8MHz BW Noise-Shaping SAR ADC Using High-Speed Switches. MWSCAS (2018)
Yongzhen Chen, Jingjing Wang, Hang Hu, Fan Ye, Junyan Ren
A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier. ISCAS (2017)
Fubiao Cao, Yongzhen Chen, Zhiyuan Dai, Fan Ye, Junyan Ren
An input buffer for 12bit 2GS/s ADC. ASICON (2017)
Yongzhen Chen, Yimin Wu, Fubiao Cao, Fan Ye, Junyan Ren
A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs. ASICON (2017)
Fubiao Cao, Yongzhen Chen, Yuefeng Cao, Fan Ye, Junyan Ren
A proved dither-injection method for memory effect in double sampling pipelined ADC. ASICON (2017)
Yuefeng Cao, Yongzhen Chen, Tianli Zhang, Fan Ye, Junyan Ren
An improved ring amplifier with process- and supply voltage-insensitive dead-zone. MWSCAS (2017)
Yimin Wu, Yongzhen Chen, Manxin Li, Fan Ye, Junyan Ren
A stacked-packaged 16-channel ADC for ultrasound application. ASICON (2017)
Shunli Ma, Guangyao Zhou, Jianbing Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren
A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. ESSCIRC (2015)
Rongjin Xu, Yongzhen Chen, Mingshuo Wang, Ning Li, Fan Ye, Junyan Ren
A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network. ASICON (2015)
Yongzhen Chen, Miguel Rodel Felipe, Yi Wang, Yajun Ha, Shu Qin Ren, Khin Mi Mi Aung
sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface. FPT (2013)
Yongzhen Chen, Chixiao Chen, Qiang Zhang, Fan Ye, Junyan Ren
A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique. ASICON (2013)