Rongjin Xu

Publication Activity (10 Years)

Years Active: 2015-2022
Publications (10 Years): 10

Top Topics

Intersymbol Interference

Frequency Response

Top Venues

IEEE J. Solid State Circuits

Publications

Rongjin Xu, Dawei Ye, Sirou Li, C.-J. Richard Shi
65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency. ISSCC (2022)
Rongjin Xu, Dawei Ye, C.-J. Richard Shi
A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction. Integr. 84 (2022)
Rongjin Xu, Dawei Ye, C.-J. Richard Shi
Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (7) (2022)
Dawei Ye, Rongjin Xu, C.-J. Richard Shi
Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain". IEEE J. Solid State Circuits 57 (2) (2022)
Dawei Ye, Yuting Tu, Wenjun Gong, Rongjin Xu, C.-J. Richard Shi
A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference. A-SSCC (2021)
Dawei Ye, Rongjin Xu, C.-J. Richard Shi
A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain. IEEE J. Solid State Circuits 56 (11) (2021)
Yuting Tu, Rongjin Xu, Dawei Ye, Liangjian Lyu, C.-J. Richard Shi
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. ISCAS (2020)
Liangjian Lyu, Dawei Ye, Rongjin Xu, Geng Mu, Heng Zhao, Yingfei Xiang, Yuting Tu, Yiyun Zhang, C.-J. Richard Shi
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission. IEEE Trans. Circuits Syst. II Express Briefs (5) (2020)
Dawei Ye, Rongjin Xu, C.-J. Richard Shi
A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity. ISSCC (2019)
Dawei Ye, Rongjin Xu, Liangjian Lyu, C.-J. Richard Shi
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. ISCAS (2019)
Rongjin Xu, Yongzhen Chen, Mingshuo Wang, Ning Li, Fan Ye, Junyan Ren
A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network. ASICON (2015)
Jingjing Wang, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren
100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array. ASICON (2015)