Chixiao Chen

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 54

Top Topics

Contour Fragments

Target Detection

Top Venues

IEEE J. Emerg. Sel. Topics Circuits Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Haozhe Zhu, Hongyi Zhang, Siqi He, Mengjie Li, Xiaoyang Zeng, Chixiao Chen
Trident-CIM: A LUT-Based Compute-in-Memory Macro With Trident Read Bit-Line and Partial Product Pruning. IEEE Trans. Circuits Syst. II Express Briefs 71 (5) (2024)
Wenning Jiang, Yunbin Luo, Peizhe Li, Ji Guo, Chixiao Chen, Qi Liu
A 13b 500MS/s Dual-Residue Pipelined-SAR ADC with One-Way Switching Capacitive Interpolation and Background Offset Calibration. CICC (2024)
Mengjie Li, Hongyi Zhang, Siqi He, Haozhe Zhu, Hao Zhang, Jinglei Liu, Jiayuan Chen, Zhenping Hu, Xiaoyang Zeng, Chixiao Chen
A 19.7 TFLOPS/W Multiply-less Logarithmic Floating-Point CIM Architecture with Error-Reduced Compensated Approximate Adder. ISCAS (2024)
Hongyi Zhang, Haozhe Zhu, Siqi He, Mengjie Li, Chengchen Wang, Xiankui Xiong, Haidong Tian, Xiaoyang Zeng, Chixiao Chen
ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test. DATE (2024)
Yinglin Yang, Yunzhengmao Wang, Tengyue Yi, Chixiao Chen, Qi Liu
A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration. Integr. 96 (2024)
Jingyi Wang, Zhangcheng Huang, Bu Chen, Hongyang Shang, Jiapei Zheng, Hankun Lv, Chixiao Chen, Qi Liu, Ming Liu
A 32×32 Flash LiDAR SPAD Sensor with Up-to-1kfps Motional Target Detection by Threshold-adaptive 2D Dynamic Vision. CICC (2024)
Shiwei Liu, Chen Mu, Hao Jiang, Yunzhengmao Wang, Jinshan Zhang, Feng Lin, Keji Zhou, Qi Liu, Chixiao Chen
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer. IEEE Trans. Very Large Scale Integr. Syst. 32 (2) (2024)
Shiwei Liu, Peizhe Li, Jinshan Zhang, Yunzhengmao Wang, Haozhe Zhu, Wenning Jiang, Shan Tang, Chixiao Chen, Qi Liu, Ming Liu
A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine. ISSCC (2023)
Xinsheng Wang, Maosong Shi, Peizhe Li, Jianwei Liu, Zhangcheng Huang, Chixiao Chen, Wenning Jiang
A 10b 1.25GS/s Residue Post-Amplified Pipelined-SAR ADC with Supply-and-Temperature Stabilized Open-Loop Residue Amplifier. ISCAS (2023)
Wenning Jiang, Yan Zhu, Chixiao Chen, Hao Xu, Qi Liu, Ming Liu, Rui Paulo Martins, Chi-Hang Chan
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier. IEEE J. Solid State Circuits 58 (10) (2023)
Jiapei Zheng, Hao Jiang, Xinkai Nie, Zhangcheng Huang, Chixiao Chen, Qi Liu
TiPU: A Spatial-Locality-Aware Near-Memory Tile Processing Unit for 3D Point Cloud Neural Network. DAC (2023)
Jie Liao, Bo Jiao, Jinshan Zhang, Shiwei Liu, Hao Jiang, Jun Tao, Wenning Jiang, Qi Liu, Lihua Zhang, Haozhe Zhu, Chixiao Chen
A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration. ISCAS (2023)
Jiangnan Yu, Fan Yang, Xiaoling Yi, Chixiao Chen, Jun Tao, Dong Xu, Xiankui Xiong, Haitao Yang
TPNoC: An Efficient Topology Reconfigurable NoC Generator. ACM Great Lakes Symposium on VLSI (2023)
Hao Jiang, Jiapei Zheng, Yunzhengmao Wang, Jinshan Zhang, Haozhe Zhu, Liangjian Lyu, Yingping Chen, Chixiao Chen, Qi Liu
A $2.53 \mu \mathrm{W}/\text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. ISCAS (2023)
Siqi He, Hongyi Zhang, Mengjie Li, Haozhe Zhu, Chixiao Chen, Qi Liu, Xiaoyang Zeng
Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation. AICAS (2023)
Chen Mu, Yunzhengmao Wang, Jiapei Zheng, Shiwei Liu, Keji Zhou, Shan Tang, Chixiao Chen, Qi Liu
A 200M-Query-Vector/s Computing-in-RRAM ADC-less k-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits. AICAS (2022)
Haozhe Zhu, Bo Jiao, Jinshan Zhang, Xinru Jia, Yunzhengmao Wang, Tianchan Guan, Shengcheng Wang, Dimin Niu, Hongzhong Zheng, Chixiao Chen, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Qi Liu, Yuan Xie, Ming Liu
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. ISSCC (2022)
Zheng Wu, Wuzhen Xie, Xiaoling Yi, Haitao Yang, Ruiyao Pu, Xiankui Xiong, Haidong Yao, Chixiao Chen, Jun Tao, Fan Yang
An Automated Compiler for RISC-V Based DNN Accelerator. ISCAS (2022)
Shunli Wang, Shuaibing Wang, Bo Jiao, Dingkang Yang, Liuzhen Su, Peng Zhai, Chixiao Chen, Lihua Zhang
CA-SpaceNet: Counterfactual Analysis for 6D Pose Estimation in Space. CoRR (2022)
Qing Wan, Changjin Wan, Huaqiang Wu, Yuchao Yang, Xiaohe Huang, Peng Zhou, Lin Chen, Tian-Yu Wang, Yi Li, Kan-Hao Xue, Yu-Hui He, Xiang-Shui Miao, Xi Li, Chenchen Xie, Houpeng Chen, Zhitang Song, Hong Wang, Yue Hao, Junyao Zhang, Jia Huang, Zheng Yu Ren, Li Qiang Zhu, Jianyu Du, Chen Ge, Yang Liu, Guanglong Ding, Ye Zhou, Su-Ting Han, Guosheng Wang, Xiao Yu, Bing Chen, Zhufei Chu, Lunyao Wang, Yinshui Xia, Chen Mu, Feng Lin, Chixiao Chen, Bojun Cheng, Yannan Xing, Weitao Zeng, Hong Chen, Lei Yu, Giacomo Indiveri, Ning Qiao
2022 roadmap on neuromorphic devices and applications research in China. Neuromorph. Comput. Eng. 2 (4) (2022)
Keji Zhou, Xinru Jia, Chenyang Zhao, Xumeng Zhang, Guangjian Wu, Chen Mu, Haozhe Zhu, Yanting Ding, Chixiao Chen, Xiaoyong Xue, Xiaoyang Zeng, Qi Liu
A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output. IEEE J. Emerg. Sel. Topics Circuits Syst. 12 (4) (2022)
Chixiao Chen, Jieming Yin, Yarui Peng, Maurizio Palesi, Wenxu Cao, Letian Huang, Amit Kumar Singh, Haocong Zhi, Xiaohang Wang
Design Challenges of Intrachiplet and Interchiplet Interconnection. IEEE Des. Test 39 (6) (2022)
Xiaoling Yi, Jiangnan Yu, Zheng Wu, Xiankui Xiong, Dong Xu, Chixiao Chen, Jun Tao, Fan Yang
NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models. ISCAS (2022)
Danfeng Zhai, Wenning Jiang, Xinru Jia, Jingchao Lan, Mingqiang Guo, Sai-Weng Sin, Fan Ye, Qi Liu, Junyan Ren, Chixiao Chen
High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Shunli Wang, Shuaibing Wang, Bo Jiao, Dingkang Yang, Liuzhen Su, Peng Zhai, Chixiao Chen, Lihua Zhang
CA-SpaceNet: Counterfactual Analysis for 6D Pose Estimation in Space. IROS (2022)
Junru Sheng, Peng Zhai, Zhiyan Dong, Xiaoyang Kang, Chixiao Chen, Lihua Zhang
Curriculum Adversarial Training for Robust Reinforcement Learning. IJCNN (2022)
Shunli Wang, Dingkang Yang, Peng Zhai, Chixiao Chen, Lihua Zhang
TSA-Net: Tube Self-Attention Network for Action Quality Assessment. CoRR (2022)
Xinru Jia, Haozhe Zhu, Yunzheng Wang, Jinshan Zhang, Feng Lin, Xiankui Xiong, Dong Xu, Chixiao Chen, Qi Liu
A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization. ISCAS (2022)
Jingying Zhang, Yang Zhao, Mingyi Chen, Chixiao Chen, Fan Ye, Liang Qi
Self-coupled MASH Delta-Sigma Modulator with Zero Optimization. ISOCC (2021)
Bo Jiao, Jinshan Zhang, Yuanyuan Xie, Shunli Wang, Haozhe Zhu, Xiaoyang Kang, Zhiyan Dong, Lihua Zhang, Chixiao Chen
A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA. ASP-DAC (2021)
Jinshan Zhang, Bo Jiao, Yunzhengmao Wang, Haozhe Zhu, Lihua Zhang, Chixiao Chen
ALPINE: An Agile Processing-in-Memory Macro Compilation Framework. ACM Great Lakes Symposium on VLSI (2021)
Liang Qi, Xinyu Qin, Sai-Weng Sin, Chixiao Chen, Fan Ye, Guoyong Shi, Guoxing Wang
Advances in Continuous-time MASH ΔΣ Modulators. ASICON (2021)
Danfeng Zhai, Chixiao Chen, Liang Qi, Fan Ye, Junyan Ren
Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration. ISOCC (2021)
Shunli Wang, Dingkang Yang, Peng Zhai, Chixiao Chen, Lihua Zhang
TSA-Net: Tube Self-Attention Network for Action Quality Assessment. ACM Multimedia (2021)
Bo Jiao, Haozhe Zhu, Jinshan Zhang, Shunli Wang, Xiaoyang Kang, Lihua Zhang, Mingyu Wang, Chixiao Chen
Computing Utilization Enhancement for Chiplet-based Homogeneous Processing-in-Memory Deep Learning Processors. ACM Great Lakes Symposium on VLSI (2021)
Yuefeng Cao, Shumin Zhang, Tianli Zhang, Yongzhen Chen, Yutong Zhao, Chixiao Chen, Fan Ye, Junyan Ren
A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (2) (2021)
Danfeng Zhai, Peizhe Li, Jiushan Zhang, Chixiao Chen, Fan Ye, Junyan Ren
Additive Neural Network Based Static and Dynamic Distortion Modeling for Prior-Knowledge-Free Nyquist ADC Characterization. MWSCAS (2021)
Min Chen, Yimin Wu, Jingchao Lan, Fan Ye, Chixiao Chen, Junyan Ren
A Calibration Scheme for Nonlinearity of the SAR-Pipelined ADCs Based on a Shared Neural Network. APCCAS (2020)
Liangjian Lyu, Yu Wang, Chixiao Chen, C.-J. Richard Shi
A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback. Integr. 70 (2020)
Haozhe Zhu, Chixiao Chen, Shiwei Liu, Qiaosha Zou, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, C.-J. Richard Shi
A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. 10 (3) (2020)
Shiwei Liu, Haozhe Zhu, Chixiao Chen, Lihua Zhang, C.-J. Richard Shi
XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping. AICAS (2020)
Yongzhen Chen, Xingchen Shen, Zhekan Ni, Jingchao Lan, Chixiao Chen, Fan Ye, Junyan Ren
A 625MS/s, 12-Bit, SAR Assisted Pipeline ADC with Effective Gain Analysis for Inter-stage Ringamps. ESSCIRC (2019)
Liangjian Lyu, Yu Wang, Chixiao Chen, C.-J. Richard Shi
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. ASP-DAC (2019)
Aili Wang, Chixiao Chen, C.-J. Richard Shi
A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time. CICC (2019)
Tianli Zhang, Yuefeng Cao, Shumin Zhang, Chixiao Chen, Fan Ye, Junyan Ren
Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR. ESSCIRC (2019)
Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, C.-J. Richard Shi
iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric. IEEE J. Emerg. Sel. Topics Circuits Syst. 9 (2) (2019)
Chixiao Chen, Huwan Peng, Xindi Liu, Hongwei Ding, C.-J. Richard Shi
Exploring the programmability for deep learning processors: from architecture to tensorization. DAC (2018)
Chixiao Chen, Hongwei Ding, Huwan Peng, Haozhe Zhu, Yu Wang, C.-J. Richard Shi
OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 8 (3) (2018)
Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, C.-J. Richard Shi
iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS. ESSCIRC (2018)
Hang Hu, Zemin Feng, Chixiao Chen, Fan Ye, Junyan Ren
High speed digital ELD compensation with hybrid thermometer coding in CT ΔΣ modulators. MWSCAS (2017)
Chixiao Chen, Hongwei Ding, Huwan Peng, Haozhe Zhu, Rui Ma, Peiyong Zhang, Xiaolang Yan, Yu Wang, Mingyu Wang, Hao Min, C.-J. Richard Shi
OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators. ESSCIRC (2017)
Aili Wang, Chixiao Chen, Chuanjin Richard Shi
Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2017)
Xiaolong Liu, Chixiao Chen, Junyan Ren, Howard C. Luong
Transformer-based varactor-less 96GHz-110GHz VCO and 89GHz-101GHz QVCO in 65nm CMOS. A-SSCC (2016)
Bingwei Jiang, Chixiao Chen, Junyan Ren, Howard C. Luong
A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network. A-SSCC (2016)
Chixiao Chen, Zemin Feng, Jun Xu, Fan Ye, Junyan Ren
An ARMA-Model-Based NTF Estimation on Continuous-Time ΔΣ Modulators. IEEE Trans. Circuits Syst. II Express Briefs (8) (2015)
Shunli Ma, Guangyao Zhou, Jianbing Jiang, Chixiao Chen, Yongzhen Chen, Fan Ye, Junyan Ren
A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system. ESSCIRC (2015)
Chixiao Chen, Jixuan Xiang, Jiang Fan, Xu Jun, Ye Fan, Junyan Ren
A 270-MS/s 6-b SAR ADC with preamplifier sharing and self-locking comparators. IEICE Electron. Express 12 (5) (2015)
Zemin Feng, Jingjing Wang, Chixiao Chen, Jun Xu, Junyan Ren
A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method. ASICON (2015)
Jingjing Wang, Rongjin Xu, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren
100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array. ASICON (2015)
Chixiao Chen, Zemin Feng, Huabin Chen, Mingshuo Wang, Jun Xu, Fan Ye, Junyan Ren
A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier. ISCAS (2014)
Guoxian Dai, Chixiao Chen, Shunli Ma, Fan Ye, Junyan Ren
A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators. ISCAS (2014)
Bei Yu, Chixiao Chen, Fan Ye, Junyan Ren
A mixed sample-time error calibration technique in time-interleaved ADCs. IEICE Electron. Express 10 (24) (2013)
Yuzhong Xiao, Chixiao Chen, Rui Wei, Fan Jiang, Jun Xu, Junyan Ren
A 80-dB DR, 10-MHz BW continuous-time sigma-delta modulator with low power comparators and switch drivers. ASICON (2013)
Yongzhen Chen, Chixiao Chen, Qiang Zhang, Fan Ye, Junyan Ren
A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique. ASICON (2013)
Zemin Feng, Chixiao Chen, Fan Ye, Jun Xu, Junyan Ren
A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator. ASICON (2013)
Fan Jiang, Chixiao Chen, Yuzhong Xiao, Jun Xu, Junyan Ren
Beyond-one-cycle loop delay CT ΔΣ modulators with proper rational NTF synthesis and time-interleaved quantizers. MWSCAS (2013)
Zhenyu Wang, Mingshuo Wang, Weiru Gu, Chixiao Chen, Fan Ye, Junyan Ren
A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2013)
Yiwen Zhang, Xiaoshi Zhu, Chixiao Chen, Fan Ye, Junyan Ren
A sample-time error calibration technique in time-interleaved ADCs with correlation-based detection and voltage-controlled compensation. APCCAS (2012)
Long Cheng, Chixiao Chen, Fan Ye, Ning Li, Junyan Ren
A digitally calibrated current-steering DAC with current-splitting array. MWSCAS (2012)
Chixiao Chen, ShengChang Cai, Jialiang Xu, Xiaoshi Zhu, Fan Ye, Junyan Ren
An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling. MWSCAS (2012)
Bei Yu, Chixiao Chen, Yu Zhu, Peng Zhang, Yiwen Zhang, Xiaoshi Zhu, Fan Ye, Junyan Ren
A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation. A-SSCC (2011)
Qianqian Ha, Fan Ye, Chixiao Chen, Xiaoshi Zhu, Mingshuo Wang, Yu-Jing Lin, Ning Li, Junyan Ren
A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application. ASICON (2011)