Chi-Hang Chan

ORCID

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 90

Top Venues

IEEE J. Solid State Circuits

ISSCC

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Yaozhong Ou, Wei-Han Yu, Ka-Fai Un, Chi-Hang Chan, Yan Zhu
A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing. IEEE Trans. Circuits Syst. II Express Briefs 71 (5) (2024)
Pengyu He, Yuanzhe Zhao, Heng Xie, Yang Wang, Shouyi Yin, Li Li, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan, Minglei Zhang
A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC. CICC (2024)
Yuefeng Cao, Minglei Zhang, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan
22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer. ISSCC (2024)
Chi-Hang Chan, Minglei Zhang, Yuefena Cao, Honazhi Zhao, Rui Paulo Martins, Yan Zhu
The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs. CICC (2024)
Chaorui Zou, Yaozhong Ou, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan, Minglei Zhang
6.8 A 256×192-Pixel 30fps Automotive Direct Time-of-Flight LiDAR Using 8× Current-Integrating-Based TIA, Hybrid Pulse Position/Width Converter, and Intensity/CNN-Guided 3D Inpainting. ISSCC (2024)
Wei Zhang, Minglei Zhang, Yan Zhu, R. P. Martins, Chi-Hang Chan
A PVT-Robust 8b 20GS/s Time-Interleaved SAR ADC with Quantization-Embedded Current-Mode Buffer and Differ-Based Dither Timing Skew Calibration. CICC (2024)
ZiXuan Xu, Kai Xing, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan
An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R. IEEE J. Solid State Circuits 59 (3) (2024)
Hongzhi Zhao, Minglei Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input. ISSCC (2023)
Hongzhi Zhao, Minglei Zhang, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan
A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC. IEEE J. Solid State Circuits 58 (12) (2023)
Wenning Jiang, Yan Zhu, Chixiao Chen, Hao Xu, Qi Liu, Ming Liu, Rui Paulo Martins, Chi-Hang Chan
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier. IEEE J. Solid State Circuits 58 (10) (2023)
Yuefeng Cao, Minglei Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer. ISSCC (2023)
Yanbo Zhang, Junyan Hao, Shubin Liu, Zhangming Zhu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
-Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping. ISSCC (2023)
Hongshuai Zhang, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan
A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator. IEEE J. Solid State Circuits 58 (12) (2023)
Yuanzhe Zhao, Minglei Zhang, Pengyu He, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
A Double-Mode Sparse Compute-In-Memory Macro with Reconfigurable Single and Dual Layer Computation. CICC (2023)
Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Rui Paulo Martins, Yan Zhu, Jan Craninckx, Chi-Hang Chan
A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Hongshuai Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
-Order Gain-Error-Shaping and NS Pipelined SAR ADC Based on a Quantization-Prediction-Unrolled Scheme. ISSCC (2023)
Junlin Zhong, Xiaofeng Yang, Rui Paulo Martins, Yan Zhu, Chi-Hang Chan
Active Area 4GHz Fully Ring-Oscillator-Based Cascaded Fractional-N PLL With Burst-Mode Sampling. IEEE Trans. Circuits Syst. II Express Briefs 70 (10) (2023)
Junyan Hao, Minglei Zhang, Yanbo Zhang, Shubin Liu, Zhangming Zhu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness. ISSCC (2023)
Minglei Zhang, Yuefeng Cao, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors. VLSI Technology and Circuits (2023)
ZiXuan Xu, Kai Xing, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
An ELDC-Free 2.78mW 20MHz-BW 75.5dB-SNDR 4th- Order CTSDM Facilitated by 2nd-Order CT NS-SAR and AC-Coupled Negative-R. CICC (2023)
Xiang-Hui Pan, Buhui Rui, Yuefeng Cao, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
A 12b 1GS/s ADC with Lightweight Input Buffer Distortion Background Calibration Achieving >75dB SFDR over PVT. CICC (2023)
Jiahao Liu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
An Entropy-Source-Preselection-Based Strong PUF With Strong Resilience to Machine Learning Attacks and High Energy Efficiency. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Lele Fang, Jiahao Liu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
LSB-Reused Protection Technique in Secure SAR ADC against Power Side-Channel Attack. AsianHOST (2022)
Yanbo Zhang, Jin Zhang, Shubin Liu, Ruixue Ding, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations. IEEE J. Solid State Circuits 57 (3) (2022)
Yi Zeng, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins
A low dropout regulator with PSR under -48dB up to 20GHz for a SARADC reference buffer. MWSCAS (2022)
Yi Zeng, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins
An Auxiliary-Loop-Enhanced Fast-Transient FVF LDO as Reference Buffer of a SAR ADC. ISCAS (2022)
Kai Xing, Wei Wang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
Hongshuai Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration. IEEE J. Solid State Circuits 57 (5) (2022)
Yu Duan, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins
Supply-Noise-Desensitized Techniques for Low Jitter RO-Based PLL Achieving ≤1.6 ps RMS Jitter Within Full-Spectrum Supply Interference. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier. IEEE J. Solid State Circuits 57 (6) (2022)
Jiahao Liu, Yuanzhe Zhao, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
A Weak PUF-Assisted Strong PUF With Inherent Immunity to Modeling Attacks and Ultra-Low BER. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Minglei Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration. VLSI Circuits (2021)
Wenning Jiang, Yan Zhu, Chi-Hang Chan, Boris Murmann, Rui Paulo Martins
A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (2) (2021)
Yanbo Zhang, Jin Zhang, Shubin Liu, Zhangming Zhu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
-Order SAR-Assisted Noise-Shaping Pipeline ADC with Gain and Offset Background Calibrations Based on Convergence Enhanced Split-Over-Time Architecture. CICC (2021)
Yan Song, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC. IEEE J. Solid State Circuits 56 (6) (2021)
Jiahao Liu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
. A-SSCC (2021)
Rui Paulo Martins, Pui-In Mak, Chi-Hang Chan, Jun Yin, Yan Zhu, Yong Chen, Yan Lu, Man-Kay Law, Sai-Weng Sin
Bird's-eye view of analog and mixed-signal chips for the 21st century. Int. J. Circuit Theory Appl. 49 (3) (2021)
Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins
Nyquist Zone in 1GS/s ADC. VLSI Circuits (2021)
Hongshuai Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration. ISSCC (2021)
Wei Wang, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins
A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization. IEEE J. Solid State Circuits 55 (6) (2020)
Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. ISSCC (2020)
Xiaofeng Yang, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins
A Calibration-Free Ring-Oscillator PLL With Gain Tracking Achieving 9% Jitter Variation Over PVT. IEEE Trans. Circuits Syst. (11) (2020)
Minglei Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input. ISSCC (2020)
Minglei Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC With <1.5-ps Uncalibrated Quantization Steps. IEEE J. Solid State Circuits 55 (12) (2020)
Yan Song, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins
A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC. IEEE J. Solid State Circuits 55 (2) (2020)
Jiahao Liu, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
A 0.04% BER Strong PUF With Cell-Bias-Based CRPs Filtering and Background Offset Calibration. IEEE Trans. Circuits Syst. (11) (2020)
Yan Song, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
9.6 A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration. ISSCC (2020)
Yanbo Zhang, Shubin Liu, Binbin Tian, Yan Zhu, Chi-Hang Chan, Zhangming Zhu
A 2nd-Order Noise-Shaping SAR ADC With Lossless Dynamic Amplifier Assisted Integrator. IEEE Trans. Circuits Syst. II Express Briefs (10) (2020)
Kai Xing, Wei Wang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SAB-ELD-Merged Integrator and 3-Stage Opamp. VLSI Circuits (2020)
Jin Zhang, Xiaoqian Ren, Shubin Liu, Chi-Hang Chan, Zhangming Zhu
An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (7) (2020)
Wenning Jiang, Yan Zhu, Minglei Zhang, Chi-Hang Chan, Rui Paulo Martins
A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier. IEEE J. Solid State Circuits 55 (2) (2020)
Xiaochao Li, Chi-Hang Chan, Qi Zhang, Yan Zhu, Rui Paulo Martins
Background Offset Calibration for Comparator Based on Temperature Drift Profile. IEEE Trans. Circuits Syst. II Express Briefs (10) (2019)
Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Xiaofeng Yang, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins
A -246dB Jitter-FoM 2.4GHz Calibration-Free Ring-Oscillator PLL Achieving 9% Jitter Variation Over PVT. ISSCC (2019)
Wei Wang, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins
A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ. ISSCC (2019)
Minglei Zhang, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins
A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques. ISSCC (2019)
Xuewei Lei, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins
A 4-b 7-µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2019)
Dezhi Xing, Yan Zhu, Chi-Hang Chan, Franco Maloberti, Seng-Pan U, Rui Paulo Martins
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2019)
Cheng Li, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins
Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2019)
Minglei Zhang, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins
A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-Enhanced Techniques. IEEE J. Solid State Circuits 54 (12) (2019)
Lai Wei, Xiang-Hui Pan, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins
Input Correlated Swap-Sampling Technique for Input Driver Power Reduction in a 12b 25MS/s SAR ADC. ISCAS (2019)
Wenning Jiang, Yan Zhu, Minglei Zhang, Chi-Hang Chan, Rui Paulo Martins
A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier. ISSCC (2019)
Wei Wang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
A 5.35-mW 10-MHz Single-Opamp Third-Order CT ΔΣ Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS. IEEE J. Solid State Circuits 53 (10) (2018)
X. Shawn Wang, Xin Jin, Jieqiong Du, Yilei Li, Yuan Du, Chien-Heng Wong, Yen-Cheng Kuan, Chi-Hang Chan, Mau-Chung Frank Chang
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (11) (2018)
Yan Zhu, Chi-Hang Chan, Rui Paulo Martins
An 11b 1GS/s Time-Interleaved ADC with Linearity Enhanced T/H. A-SSCC (2018)
Guan-Cheng Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area. IEEE Trans. Very Large Scale Integr. Syst. 26 (11) (2018)
Guan-Cheng Wang, Cheng Li, Yan Zhu, Jianyu Zhong, Yan Lu, Chi-Hang Chan, Rui Paulo Martins
Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2018)
Chi-Hang Chan, Yan Zhu, Zi-Hao Zheng, Rui Paulo Martins
A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end. ESSCIRC (2018)
Yan Zhu, Chi-Hang Chan, Zi-Hao Zheng, Cheng Li, Jianyu Zhong, Rui Paulo Martins
10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2018)
Chi-Hang Chan, Yan Zhu, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration. IEEE J. Solid State Circuits 53 (3) (2018)
Yan Song, Chi-Hang Chan, Yan Zhu, Li Geng, Seng-Pan U, Rui Paulo Martins
Passive Noise Shaping in SAR ADC With Improved Efficiency. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
Yan Song, Yan Zhu, Chi-Hang Chan, Li Geng, Rui Paulo Martins
A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ∑Δ ADC Based on the Pipelined-SAR Structure. VLSI Circuits (2018)
Wenning Jiang, Yan Zhu, Chi-Hang Chan, Boris Murmann, Seng-Pan U, Rui Paulo Martins
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler. A-SSCC (2018)
Xiaofeng Yang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2018)
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2017)
Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Chi-Hang Chan, Yan Zhu, Cheng Li, Wai-Hong Zhang, Iok-Meng Ho, Lai Wei, Seng-Pan U, Rui Paulo Martins
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration. IEEE J. Solid State Circuits 52 (10) (2017)
Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins
16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration. ISSCC (2017)
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Boris Murmann, Seng-Pan U, Rui Paulo Martins
Metastablility in SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs (2) (2017)
Guan-Cheng Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC. ESSCIRC (2017)
Wei Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS. A-SSCC (2017)
Arshad Hussain, Sai-Weng Sin, Chi-Hang Chan, Ben Seng-Pan U, Franco Maloberti, Rui Paulo Martins
Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Dezhi Xing, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, Rui Paulo Martins
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
With Full-Calibration-Integrated Pipelined-SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2017)
Yan Zhu, Chi-Hang Chan, Si-Seng Wong, Seng-Pan U, Rui Paulo Martins
Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC. IEEE Trans. Very Large Scale Integr. Syst. 24 (3) (2016)
Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
pipelined-SAR ADC with merged-residue DAC for noise reduction. ESSCIRC (2016)
Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS. IEEE J. Solid State Circuits 51 (5) (2016)
Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Chon-Lam Lio, Seng-Pan U, Rui Paulo Martins
60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages. A-SSCC (2016)
Jianwei Liu, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC. IEEE Trans. Very Large Scale Integr. Syst. 24 (7) (2016)
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC. IEEE J. Solid State Circuits 51 (2) (2016)
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS. ISSCC (2015)
Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation. A-SSCC (2015)
Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. IEEE Trans. Very Large Scale Integr. Syst. 22 (2) (2014)
Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC. ESSCIRC (2014)
Wen-Lan Wu, Yan Zhu, Li Ding, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. ISCAS (2013)
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS. IEEE J. Solid State Circuits 48 (9) (2013)
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. VLSIC (2012)
Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC. VLSIC (2012)
Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation. IEEE J. Solid State Circuits 47 (11) (2012)
He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. IEEE J. Solid State Circuits 47 (11) (2012)

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Publication Activity (10 Years)

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Chi-Hang Chan