10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS.
Yan ZhuChi-Hang ChanZi-Hao ZhengCheng LiJianyu ZhongRui Paulo MartinsPublished in: IEEE Trans. Circuits Syst. I Regul. Pap. (2018)
Keyphrases
- analog to digital converter
- cmos technology
- silicon on insulator
- synthetic aperture radar
- metal oxide semiconductor
- nm technology
- sar images
- low power
- linear array
- single chip
- signal subspace
- power consumption
- low cost
- high speed
- data flow
- analog vlsi
- image sensor
- low voltage
- image reconstruction
- power supply
- circuit design
- sea ice
- cmos image sensor
- sar imagery
- image processing
- real time
- automatic target recognition
- mixed signal
- parameter estimation
- x ray
- phased array
- vlsi circuits
- delay insensitive
- optical images