Seng-Pan U

Publication Activity (10 Years)

Years Active: 1998-2021
Publications (10 Years): 55

Top Topics

Analog To Digital Converter

Fully Integrated

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE J. Solid State Circuits

Publications

Syed Muhammad Abubakar, Yue Yin, Songyao Tan, Hanjun Jiang, Zhihua Wang, Seng-Pan U, Wen Jia
A 2.52 μΑ Wearable Single Lead Ternary Neural Network Based Cardiac Arrhythmia Detection Processor. ISCAS (2021)
Yue Yin, Syed Muhammad Abubakar, Songyao Tan, Jiahua Shi, Peilin Yang, Wendi Yang, Hanjun Jiang, Zhihua Wang, Wen Jia, Seng-Pan U
A 2.63 μW ECG Processor With Adaptive Arrhythmia Detection and Data Compression for Implantable Cardiac Monitoring Device. IEEE Trans. Biomed. Circuits Syst. 15 (4) (2021)
Yue Yin, Syed Muhammad Abubakar, Songyao Tan, Hanjun Jiang, Zhihua Wang, Seng-Pan U, Wen Jia
A 17.7-pJ/Cycle ECG Processor for Arrhythmia Detection with High Immunity to Power Line Interference and Baseline Drift. A-SSCC (2020)
Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS. IEEE J. Solid State Circuits 54 (4) (2019)
Dezhi Xing, Yan Zhu, Chi-Hang Chan, Franco Maloberti, Seng-Pan U, Rui Paulo Martins
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2019)
Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS. A-SSCC (2019)
Junhao Liang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins, Hanjun Jiang
A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator. A-SSCC (2019)
Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek, Yan Zhu, Seng-Pan U
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26 (3) (2018)
Mo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins
An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator. IEEE J. Solid State Circuits 53 (1) (2018)
Junmin Jiang, Yan Lu, Xun Liu, Wing-Hung Ki, Philip K. T. Mok, Seng-Pan U, Rui Paulo Martins
A dual-output SC converter with dynamic power allocation for multicore application processors. ASP-DAC (2018)
Guan-Cheng Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area. IEEE Trans. Very Large Scale Integr. Syst. 26 (11) (2018)
Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS. VLSI Circuits (2018)
Fangyu Mao, Yan Lu, Seng-Pan U, Rui Paulo Martins
A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems. VLSI-DAT (2018)
Chi-Hang Chan, Yan Zhu, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration. IEEE J. Solid State Circuits 53 (3) (2018)
Yan Song, Chi-Hang Chan, Yan Zhu, Li Geng, Seng-Pan U, Rui Paulo Martins
Passive Noise Shaping in SAR ADC With Improved Efficiency. IEEE Trans. Very Large Scale Integr. Syst. 26 (2) (2018)
Fangyu Mao, Yan Lu, Jie Lin, Chenchang Zhan, Seng-Pan U, Rui Paulo Martins
A Single-Stage Current-Mode Active Rectifier with Accurate Output-Current Regulation for IoT. ISCAS (2018)
Wei Wei Qin, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
Quick and cost-efficient A/D converter static characterization using low-precision testing signal. Microelectron. J. 74 (2018)
Wenning Jiang, Yan Zhu, Chi-Hang Chan, Boris Murmann, Seng-Pan U, Rui Paulo Martins
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler. A-SSCC (2018)
Xiaofeng Yang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2018)
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2017)
Kostas Doris, David Robertson, Seung-Tak Ryu, Seng-Pan U
F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX. ISSCC (2017)
Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations. IEEE Trans. Very Large Scale Integr. Syst. 25 (1) (2017)
Junmin Jiang, Yan Lu, Wing-Hung Ki, Seng-Pan U, Rui Paulo Martins
20.5 A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS. ISSCC (2017)
Chi-Hang Chan, Yan Zhu, Cheng Li, Wai-Hong Zhang, Iok-Meng Ho, Lai Wei, Seng-Pan U, Rui Paulo Martins
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration. IEEE J. Solid State Circuits 52 (10) (2017)
U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
A 5-bit 2 GS/s binary-search ADC with charge-steering comparators. A-SSCC (2017)
Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins
16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration. ISSCC (2017)
Liang Qi, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins
A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2017)
Chi-Wa U, Chi-Seng Lam, Man-Kay Law, Sai-Weng Sin, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins
CCM operation analysis and parameters design of Negative Output Elementary Luo Converter for ripple suppression. IECON (2017)
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Boris Murmann, Seng-Pan U, Rui Paulo Martins
Metastablility in SAR ADCs. IEEE Trans. Circuits Syst. II Express Briefs (2) (2017)
Guan-Cheng Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC. ESSCIRC (2017)
Wei Wang, Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS. A-SSCC (2017)
Mo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins
22.4 A reconfigurable bidirectional wireless power transceiver with maximum-current charging mode and 58.6% battery-to-battery efficiency. ISSCC (2017)
Ziyang Luo, Yan Lu, Mo Huang, Junmin Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A sub-1V 78-nA bandgap reference with curvature compensation. Microelectron. J. 63 (2017)
Xia Du, Chi-Seng Lam, Sai-Weng Sin, Man-Kay Law, Franco Maloberti, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins
A digital PWM controlled KY step-up converter based on frequency domain ΣΔ ADC. ISIE (2017)
Mo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins
20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control. ISSCC (2017)
Yan Lu, Haojuan Dai, Mo Huang, Man-Kay Law, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs (2) (2017)
Dezhi Xing, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, Rui Paulo Martins
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
With Full-Calibration-Integrated Pipelined-SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2017)
Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation. IEEE Trans. Circuits Syst. II Express Briefs (7) (2016)
Yan Zhu, Chi-Hang Chan, Si-Seng Wong, Seng-Pan U, Rui Paulo Martins
Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC. IEEE Trans. Very Large Scale Integr. Syst. 24 (3) (2016)
Jianyu Zhong, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
pipelined-SAR ADC with merged-residue DAC for noise reduction. ESSCIRC (2016)
Yuan Ren, Sai-Weng Sin, Chi-Seng Lam, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins
A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controller. A-SSCC (2016)
Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS. IEEE J. Solid State Circuits 51 (5) (2016)
Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Chon-Lam Lio, Seng-Pan U, Rui Paulo Martins
60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages. A-SSCC (2016)
Jianwei Liu, Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC. IEEE Trans. Very Large Scale Integr. Syst. 24 (7) (2016)
Lei Qiu, Kai Tang, Yan Zhu, Liter Siek, Yuanjin Zheng, Seng-Pan U
A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration. A-SSCC (2016)
Mo Huang, Yan Lu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Wing-Hung Ki
Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators. IEEE Trans. Circuits Syst. II Express Briefs (9) (2016)
Mo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins
A digital LDO with transient enhancement and limit cycle oscillation reduction. APCCAS (2016)
Wei Li, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A 94-dB DR, 105-Hz bandwidth interface circuit for inertial navigation applications. ISIC (2016)
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC. IEEE J. Solid State Circuits 51 (2) (2016)
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS. ISSCC (2015)
Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation. A-SSCC (2015)
Jianyu Zhong, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2015)
Yan Lu, Junmin Jiang, Wing-Hung Ki, C. Patrick Yue, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors. ISSCC (2015)
Da Feng, Franco Maloberti, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators. ISCAS (2014)
Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. IEEE Trans. Very Large Scale Integr. Syst. 22 (2) (2014)
Yan Zhu, Chi-Hang Chan, Seng-Pan U, Rui Paulo Martins
An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC. ESSCIRC (2014)
Li Ding, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A background gain- calibration technique for low voltage pipelined ADCs based on nonlinear interpolation. MWSCAS (2013)
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS. IEEE J. Solid State Circuits 48 (9) (2013)
Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. IEEE J. Solid State Circuits 48 (8) (2013)
Yun Du, Tao He, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators. APCCAS (2012)
Chi-Hang Chan, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. VLSIC (2012)
Wen-Lan Wu, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array. APCCAS (2012)
Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC. VLSIC (2012)
Tao He, Yun Du, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity. APCCAS (2012)
Chen-Yan Cai, Yang Jiang, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
An ELD tracking compensation technique for active-RC CT ΣΔ modulators. MWSCAS (2012)
Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation. A-SSCC (2011)
Si-Seng Wong, U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators. A-SSCC (2011)
Arshad Hussain, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
Hybrid loopfilter sigma-delta modulator with NTF zero compensation. ISOCC (2011)
Chi-Hang Chan, Yan Zhu, U. Fat Chio, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS. A-SSCC (2011)
Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators. APCCAS (2010)
Sai-Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi-Hang Chan, U. Fat Chio, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. ESSCIRC (2010)
Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 μm CMOS with minimised supply headroom. IET Circuits Devices Syst. 4 (1) (2010)
Kim-Fai Wong, Ka-Ian Lei, Seng-Pan U, Rui Paulo da Silva Martins
A 1-V 90dB DR audio stereo DAC with embedding headphone driver. APCCAS (2008)
He Gong Wei, U. Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
A process- and temperature- insensitive current-controlled delay generator for sampled-data systems. APCCAS (2008)
Ngai Kong, Seng-Pan U, Rui Paulo Martins
A novel CMOS switched-current mode sequential shift forward inference circuit for fuzzy logic controller. APCCAS (2008)
Li Ding, Sio Chan, Kim-Fai Wong, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique. APCCAS (2008)
U. Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs. APCCAS (2008)
Pui-In Mak, Seng-Pan U, Rui Paulo Martins
Experimental 1-V flexible-IF CMOS analoguebaseband chain for IEEE 802.11a/b/g WLAN receivers. IET Circuits Devices Syst. 1 (6) (2007)
Pui-In Mak, Seng-Pan U, Rui Paulo Martins
A 1-V transient-free and DC-offset-canceled PGA with a 17.1-MHz constant bandwidth over 52-dB control range in 0.35-μm CMOS. CICC (2005)
Pui-In Mak, Seng-Pan U, Rui Paulo Martins
Two-step channel selection-a novel technique for reconfigurable multistandard transceiver front-ends. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2005)
Seng-Pan U, Rui Paulo Martins, José E. Franca
A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μ hboxm CMOS. IEEE J. Solid State Circuits 39 (1) (2004)
Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins
Quantitative noise analysis of jitter-induced nonuniformly sampled-and-held signals. ICASSP (6) (2003)
Pui-In Mak, Seng-Pan U, Rui Paulo Martins
A front-to-back-end modeling of I/Q mismatch effects in a complex-IF receiver for image-rejection enhancement. ICECS (2003)
Pui-In Mak, Chi-sam Sou, Seng-Pan U, Rui Paulo Martins
Frequency-downconversion and IF channel selection A-DQS sample-and-hold pair for two-step-channel-select low-IF receiver. ICECS (2003)
João Risques, Jorge Duarte, Vasco Amaro, Seng-Pan U, Kuok Vai Chiang, Ka Fai Chang, Keng Chong Lai
A very area/power efficient mixed signal circuit for voice signal processing in 0.18 digital technology. ESSCIRC (2003)
Fan Lou, Seng-Pan U, Rui Paulo Martins
N-path multirate sigma-delta modulator for high-frequency applications. ICECS (2002)
Seng-Pan U, Rui Paulo Martins, José E. Franca
A linear-phase halfband SC video interpolation filter with coefficient-sharing and spread-reduction. ISCAS (2000)
Seng-Pan U, Rui Paulo Martins, José E. Franca
A novel half-band SC architecture for efficient analog impulse sampled interpolation. ICECS (1998)