He Gong Wei

Publication Activity (10 Years)

Years Active: 2008-2020
Publications (10 Years): 4

Top Topics

Power Consumption

Camera Calibration

Top Venues

IEEE J. Solid State Circuits

Publications

Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration. IEEE J. Solid State Circuits 55 (3) (2020)
Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins
A 5 GS/s 29 mW Interleaved SAR ADC With 48.5 dB SNDR Using Digital-Mixing Background Timing-Skew Calibration for Direct Sampling Applications. IEEE Access 8 (2020)
Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins
A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing. VLSI Circuits (2019)
Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins
A 10b 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration. CICC (2019)
Guohe Yin, He Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins
4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS. ESSCIRC (2012)
He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. IEEE J. Solid State Circuits 47 (11) (2012)
He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. ISSCC (2011)
U-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC. IEEE Trans. Circuits Syst. II Express Briefs (8) (2010)
Sai-Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi-Hang Chan, U. Fat Chio, Seng-Pan U, Rui Paulo Martins, Franco Maloberti
An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. ESSCIRC (2010)
He Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (1) (2010)
Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs. VLSI Design 2010 (2010)
Guohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Zhihua Wang
An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications. ICECS (2010)
He Gong Wei, U. Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
A process- and temperature- insensitive current-controlled delay generator for sampled-data systems. APCCAS (2008)
Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. ICECS (2008)
He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. ISCAS (2008)
U. Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins
A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs. APCCAS (2008)