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A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs.
U. Fat Chio
He Gong Wei
Yan Zhu
Sai-Weng Sin
Seng-Pan U
Rui Paulo da Silva Martins
Published in:
APCCAS (2008)
Keyphrases
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high speed
asynchronous circuits
low power
logic programming
synthetic aperture radar
frame rate
classical logic
sar images
modal logic
high speed networks
proof theory
real time
digital circuits
predicate logic
automatic target recognition
maximum likelihood
synthetic aperture radar images
shift register