Seng-Pan U.

Publication Activity (10 Years)

Years Active: 1996-2018
Publications (10 Years): 1

Top Topics

Power Consumption

Synthetic Aperture Radar Images

Top Venues

IEEE J. Solid State Circuits

Publications

Fangyu Mao, Yan Lu, Seng-Pan U., Rui Paulo Martins
A reconfigurable cross-connected wireless-power transceiver for bidirectional device-to-device charging with 78.1% total efficiency. ISSCC (2018)
Wen-Lan Wu, Yan Zhu, Li Ding, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. ISCAS (2013)
Yun Du, Tao He, Yang Jiang, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW. ISCAS (2013)
Tao He, Yang Jiang, Yun Du, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer. ISCAS (2012)
Guohe Yin, He Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins
4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS. ESSCIRC (2012)
Yan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation. IEEE J. Solid State Circuits 47 (11) (2012)
Rui Wang, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins
A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique. ESSCIRC (2012)
He Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. IEEE J. Solid State Circuits 47 (11) (2012)
Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC. CICC (2012)
He Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. ISSCC (2011)
U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. ESSCIRC (2011)
U-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC. IEEE Trans. Circuits Syst. II Express Briefs (8) (2010)
Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. IEEE J. Solid State Circuits 45 (6) (2010)
Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. ISCAS (2010)
He Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (1) (2010)
Li Ding, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs. APCCAS (2010)
Yang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators. ICECS (2010)
Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs. VLSI Design 2010 (2010)
Guohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Zhihua Wang
An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications. ICECS (2010)
Pui-In Mak, Seng-Pan U., Rui Paulo Martins
On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2008)
Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2008)
Yan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. ICECS (2008)
Sai-Weng Sin, U-Fat Chio, Seng-Pan U., Rui Paulo Martins
Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch. IEEE Trans. Circuits Syst. II Express Briefs (7) (2008)
He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. ISCAS (2008)
Weng-leng Mok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins
A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC. ISCAS (2007)
Kin-Sang Chio, Seng-Pan U., Rui Paulo Martins
A dual-mode low-distortion sigma-delta modulator with relaxing comparator accuracy. ISCAS (2006)
Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits. ISCAS (2006)
Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications. ISCAS (2006)
Chon-In Lao, Seng-Pan U., Rui Paulo Martins
A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling mismatch-free resonator. ISCAS (2006)
Pui-In Mak, Seng-Pan U., Rui Paulo Martins
Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers. ISCAS (2006)
Ka-Hou Ao Ieong, Seng-Pan U., Rui Paulo Martins
A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique. APCCAS (2006)
Ka-Hou Ao Ieong, Chong-Yin Fok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins
A frequency up-conversion and two-step channel selection embedded CMOS D/A interface. ISCAS (1) (2005)
Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. ISCAS (2) (2005)
Chon-In Lao, Seng-Pan U., Rui Paulo Martins
A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators. ISCAS (4) (2005)
Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. ISCAS (2) (2005)
Kin-Sang Chio, Seng-Pan U., Rui Paulo Martins
A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA. ISCAS (4) (2005)
Pui-In Mak, Seng-Pan U., Rui Paulo Martins
A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applications. ISCAS (4) (2004)
Pui-In Mak, Kin-Kwan Ma, Weng-leng Mok, Chi-sam Sou, Kit-man Ho, Cheng-Man Ng, Seng-Pan U., Rui Paulo Martins
An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver. ISCAS (1) (2004)
Pui-In Mak, Man-Chung Wong, Seng-Pan U.
A 3D PWM control, H-bridge tri-level inverter for power quality compensation in three-phase four-wired systems. ISCAS (5) (2004)
Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins
A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems. ISCAS (1) (2004)
Seng-Pan U., Sai-Weng Sin, Rui Paulo Martins
Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects. IEEE Trans. Instrum. Meas. 53 (4) (2004)
Chon-In Lao, Ho-leng Leong, Kuoi-Fok Au, Kuok-Hang Mok, Seng-Pan U., Rui Paulo Martins
A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp SC resonator with double-sampling. ISCAS (1) (2003)
Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, José E. Franca
Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output. ISCAS (1) (2003)
Seng-Pan U., Rui Paulo Martins, José E. Franca
Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems. ISCAS (4) (2002)
Seng-Pan U., Rui Paulo Martins, José E. Franca
A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems. ISCAS (1) (2001)
Seng-Pan U., Rui Paulo Martins, José E. Franca
High-frequency low-power multirate SC realizations for NTSC/PAL digital video filtering. ISCAS (1) (2001)
Seng-Pan U., Rui Paulo Martins, José E. Franca
High performance multirate SC circuits with predictive correlated double sampling technique. ISCAS (2) (1999)
Seng-Pan U., Rui Paulo Martins, José E. Franca
Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity. ISCAS (2) (1999)
Seng-Pan U., Rui Paulo Martins, José E. Franca
New impulse sampled IIR switched-capacitor interpolators. ICECS (1996)