An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver.
Pui-In MakKin-Kwan MaWeng-leng MokChi-sam SouKit-man HoCheng-Man NgSeng-Pan U.Rui Paulo MartinsPublished in: ISCAS (1) (2004)
Keyphrases
- low cost
- multiple output
- channel estimation
- back end
- multi channel
- high speed
- power supply
- amplitude modulation
- fading channels
- communication channels
- physical layer
- multiple input multiple output
- low power
- power consumption
- analog to digital converter
- structured light
- selection algorithm
- multiple input
- false alarm probability