An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS.
Yan ZhuChi-Hang ChanSeng-Pan URui Paulo MartinsPublished in: IEEE J. Solid State Circuits (2016)
Keyphrases
- analog to digital converter
- cmos technology
- silicon on insulator
- nm technology
- synthetic aperture radar
- metal oxide semiconductor
- low power
- sar images
- single chip
- low cost
- high speed
- power consumption
- linear array
- power supply
- signal subspace
- data flow
- circuit design
- image reconstruction
- parameter estimation
- image sensor
- analog vlsi
- sar imagery
- vlsi circuits
- image processing
- multiple sclerosis
- pac man
- multiscale
- multiresolution
- maximum likelihood
- parallel processing
- low voltage
- parallel architecture