Hao Xu

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 16

Top Topics

Design Methodology

Analog To Digital Converter

Phase Locked Loop

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE J. Solid State Circuits

Publications

Hao Xu, Junyan Bi, Tenghao Zou, Weitao He, Yaxin Zeng, Junjie Gu, Ziyang Jiao, Shubin Liu, Zhangming Zhu, Na Yan
5.1 A 5-to-16GHz Reconfigurable Quadrature Receiver with 50% Duty-Cycle LO and IQ-Leakage Suppression. ISSCC (2024)
Yan Liu, Haoyuan Gao, Hao Xu, Ping Lu, Na Yan
A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (2) (2024)
Yizhuo Wang, Hao Xu, Guoyu Li, Shuai Liu, Yan Liu, Rui Yin, Hui Pan, Na Yan
An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS. CICC (2024)
Hao Xu, Shujiang Ji, Yizhuo Wang, Xinyi Lin, Hao Min, Na Yan
Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (8) (2024)
Wenning Jiang, Yan Zhu, Chixiao Chen, Hao Xu, Qi Liu, Ming Liu, Rui Paulo Martins, Chi-Hang Chan
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier. IEEE J. Solid State Circuits 58 (10) (2023)
Yizhuo Wang, Jiahe Shi, Hao Xu, Shujiang Ji, Yiyun Mao, Tenghao Zou, Jun Tao, Hao Min, Na Yan
Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL. IEEE J. Solid State Circuits 58 (8) (2023)
Peifang Wu, Yan Liu, Xi Feng, Hao Xu, Na Yan
A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS. ASICON (2023)
Xinyi Lin, Hao Xu, Dejian Li, Na Yan
A High Speed, Low Power and Low Phase Noise Divider for Wideband Application. ASICON (2023)
Yiyun Mao, Haoyuan Gao, Dejian Li, Hao Xu, Na Yan
An ADPLL Design Model Based on LoRa IoT Application. ASICON (2023)
Yaxin Zeng, Hao Xu, Xi Feng, Na Yan
Analysis and Modeling of Non-ideal Effects in SAR ADC. ASICON (2023)
Tenghao Zou, Hao Xu, Yizhuo Wang, Weitian Liu, Tingting Han, Mi Tian, Weiqiang Zhu, Na Yan
A 6-12 GHz Wideband Low-Noise Amplifier With 0.8-1.5 dB NF and ±0.75 dB Ripple Enabled by the Capacitor Assisting Triple-Winding Transformer. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (7) (2023)
Jialong Xue, Tenghao Zou, Hao Xu, Tingting Han, Mi Tian, Weiqiang Zhu, Zhijian Li, Na Yan
A 6-18GHz Low-Noise Amplifier Using Noise Canceling Technique in 130-nm CMOS PD-SOI. ICTA (2022)
Tetsuya Iizuka, Hao Xu, Asad A. Abidi
A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW. ESSCIRC (2021)
Hao Xu, Asad A. Abidi
Analysis and Design of Regenerative Comparators for Low Offset and Noise. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2019)
Dihang Yang, Asad A. Abidi, Hooman Darabi, Hao Xu, David Murphy, Hao Wu, Zhaowen Wang
A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs. ISSCC (2019)
Hao Xu, Asad A. Abidi
Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2017)
David Murphy, Hooman Darabi, Hao Xu
A Noise-Cancelling Receiver Resilient to Large Harmonic Blockers. IEEE J. Solid State Circuits 50 (6) (2015)
David Murphy, Hooman Darabi, Hao Xu
3.6 A noise-cancelling receiver with enhanced resilience to harmonic blockers. ISSCC (2014)
Asad A. Abidi, Hao Xu
Understanding the regenerative comparator circuit. CICC (2014)