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An 8-14GHz 180fs-rms DTC-Less Fractional ADPLL with ADC-Based Direct Phase Digitization in 40nm CMOS.
Yizhuo Wang
Hao Xu
Guoyu Li
Shuai Liu
Yan Liu
Rui Yin
Hui Pan
Na Yan
Published in:
CICC (2024)
Keyphrases
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high speed
user friendly
power consumption
phase locked loop
low power
cmos technology
nm technology
analog to digital converter
single chip
low cost
silicon on insulator
metal oxide semiconductor
circuit design
feature selection
power supply
analog vlsi
frequency band
parallel processing