Yong Chen

ORCID

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 97

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Access

Publications

Tian Siang Ho, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Yong Chen, Pui-In Mak, Rui Paulo Martins
Extended Power Dynamic Range and Enhanced Power Conversion Efficiency of a Switched-Capacitor DC-DC Converter: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 71 (3) (2024)
Yunbo Huang, Yong Chen, Zunsong Yang, Rui Paulo Martins, Pui-In Mak
5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur. ISSCC (2024)
Xinyu Shen, Zhao Zhang, Yong Chen, Yixi Li, Yidan Zhang, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
12.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation. CICC (2024)
Hao Wu, Yong Chen, Yiyang Yuan, Jinshan Yue, Xiangqu Fu, Qirui Ren, Qing Luo, Pui-In Mak, Xinghua Wang, Feng Zhang
A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (2) (2024)
Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (7) (2023)
Yixi Li, Zhao Zhang, Yong Chen, Xinyu Shen, Zhao Zhang, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM. A-SSCC (2023)
Roberto Rubino, Francesco Musolino, Yong Chen, Anna Richelli, Paolo Crovetti
A 880 nW, 100 kS/s, 13 bit Differential Relaxation-DAC in 180 nm. PRIME (2023)
Yuchen Wei, Shiheng Yang, Yueduo Liu, Rongxin Bao, Zihao Zhu, Jiahui Lin, Zehao Zhang, Yong Chen, Jun Yin, Pui-In Mak, Qiang Li
0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network. IEEE Trans. Very Large Scale Integr. Syst. 31 (8) (2023)
Xiangqu Fu, Qirui Ren, Hao Wu, Feibin Xiang, Qing Luo, Jinshan Yue, Yong Chen, Feng Zhang
ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Xi Wang, Dong Wei, Zhiyang Zhang, Tianxiang Wu, Xu Chen, Yong Chen, Junyan Ren, Shunli Ma
A 90- to 115-GHz superheterodyne receiver front-end for W-band imaging system in 28-nm complementary metal-oxide-semiconductor. Int. J. Circuit Theory Appl. 51 (4) (2023)
Alexander Choo Chia Chun, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Yong Chen, Saad Mekhilef, Pui-In Mak, Rui Paulo Martins
A High-Performance Dual-Topology CMOS Rectifier With 19.5-dB Power Dynamic Range for RF-Based Hybrid Energy Harvesting. IEEE Trans. Very Large Scale Integr. Syst. 31 (8) (2023)
Jack Kee Yong, Wen Xun Lian, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Gabriel Chong, Nai Shyan Lai, Yong Chen, Pui-In Mak, Rui Paulo Martins
A Fully Integrated CMOS Tri-Band Ambient RF Energy Harvesting System for IoT Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Wen Xun Lian, Harikrishnan Ramiah, Gabriel Chong, Kishore Kumar Pakkirisami Churchill, Nai Shyan Lai, Saad Mekhilef, Yong Chen, Pui-In Mak, Rui Paulo Martins
A Fully-Integrated CMOS Dual-Band RF Energy Harvesting Front-End Employing Adaptive Frequency Selection. IEEE Access 11 (2023)
Jack Kee Yong, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Gabriel Chong, Saad Mekhilef, Nai Shyan Lai, Yong Chen, Pui-In Mak, Rui Paulo Martins
A Subthreshold Operation Series-Parallel Charge Pump Incorporating Dynamic Source-Fed Oscillator for Wide-Input-Voltage Energy Harvesting Application. IEEE Access 11 (2023)
Hao Guo, Yong Chen, Yunbo Huang, Pui-In Mak, Rui Paulo Martins
An 83.3-to-104.7GHz Harmonic-Extraction VCO Incorporating Multi-Resonance, Multi-Core, and Multi-Mode (3M) Techniques Achieving -124dBc/Hz Absolute PN and 190.7dBc/Hz $\text{FoM}_{\mathrm{T}}$. ISSCC (2023)
Yujia Wang, Jincheng Zhang, Yong Chen, Junyan Ren, Shunli Ma
A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique. IEEE Trans. Very Large Scale Integr. Syst. 31 (2) (2023)
Yunbo Huang, Yong Chen, Pui-In Mak, Rui Paulo Martins
Universal Stability Criterion for Type-I Sampling Phase-Locked Loops. IEEE Trans. Circuits Syst. II Express Briefs 70 (4) (2023)
Yunbo Huang, Yong Chen, Bo Zhao, Pui-In Mak, Rui Paulo Martins
Jitter, -258.7-dB FOM, and -75.17-dBc Reference Spur. IEEE Trans. Very Large Scale Integr. Syst. 31 (2) (2023)
Li Fang Lai, Harikrishnan Ramiah, Tan Yee Chyan, Nai Shyan Lai, Chee-Cheow Lim, Yong Chen, Pui-In Mak, Rui Paulo Martins
Design Trends and Perspectives of Digital Low Dropout Voltage Regulators for Low Voltage Mobile Applications: A Review. IEEE Access 11 (2023)
Yi Chen Lee, Harikrishnan Ramiah, Alexander Choo Chia Chun, Kishore Kumar Pakkirisami Churchill, Nai Shyan Lai, Chee-Cheow Lim, Yong Chen, Pui-In Mak, Rui Paulo Martins
High-Performance Multiband Ambient RF Energy Harvesting Front-End System for Sustainable IoT Applications - A Review. IEEE Access 11 (2023)
Chenghao Zhang, Jiangbo Wei, Yong Chen, Maliang Liu, Yintang Yang
3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS. IEEE J. Solid State Circuits 58 (11) (2023)
Sikai Chen, Mingyang You, Yunqi Yang, Ye Jin, Ziyi Lin, Yihong Li, Leliang Li, Guike Li, Yujun Xie, Zhao Zhang, Binhao Wang, Ningfeng Tang, Faju Liu, Zheyu Fang, Jian Liu, Nanjian Wu, Yong Chen, Liyuan Liu, Ninghua Zhu, Ming Li, Nan Qi
A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (11) (2023)
Kishore Kumar Pakkirisami Churchill, Harikrishnan Ramiah, Alexander Choo Chia Chun, Gabriel Chong, Yong Chen, Pui-In Mak, Rui Paulo Martins
A Reconfigurable CMOS Stack Rectifier With 22.8-dB Dynamic Range Achieving 47.91% Peak PCE for IoT/WSN Application. IEEE Trans. Very Large Scale Integr. Syst. 31 (10) (2023)
Xiangdong Feng, Yuxuan Luo, Tianyi Cai, Yangfan Xuan, Yunshan Zhang, Yili Shen, Changgui Yang, Qijing Xiao, Yong Chen, Bo Zhao
/ Channel by Noise-Orthogonalizing and Pad-Sharing Techniques. CICC (2023)
Yunbo Huang, Yong Chen, Kaiyuan Yang, Paolo Crovetti, Pui-In Mak, Rui Paulo Martins
A 28-nm 368-fJ/Cycle, 0.43%/V Supply-Sensitivity, FLL-Based RC Oscillator Featuring Positive-TC-Only Resistors and ΔΣM-Based Trimming. IEEE Trans. Circuits Syst. II Express Briefs 70 (11) (2023)
Lin Wang, Yong Chen, Chaowei Yang, Xionghui Zhou, Mei Han, Crovetti Paolo Stefano, Pui-In Mak, Rui Paulo Martins
A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation. Int. J. Circuit Theory Appl. 51 (5) (2023)
Alexander Choo Chia Chun, Yi Chen Lee, Harikrishnan Ramiah, Yong Chen, Pui-In Mak, Rui Paulo Martins
A High-PCE Range-Extension CMOS Rectifier Employing Advanced Topology Amalgamation Technique for Ambient RF Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs 70 (10) (2023)
Qirui Ren, Qiang Huo, Zhisheng Chen, Qi Gao, Yiming Wang, Yiming Yang, Hao Wu, Xiangqu Fu, Xiaoxin Xu, Qing Luo, Jianfeng Gao, Chengying Chen, Xiaojin Zhao, Dengyun Lei, Xinghua Wang, Feng Zhang, Yong Chen, Pui-In Mak
A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF. IEEE Trans. Very Large Scale Integr. Syst. 31 (2) (2023)
Yunbo Huang, Yong Chen, Chaowei Yang, Pui-In Mak, Rui Paulo Martins
-Harmonic Output. ISCAS (2023)
Yunbo Huang, Yong Chen, Bo Zhao, Pui-In Mak, Rui Paulo Martins
Jitter, -260.2-dB FOM, and -70.96-dBc Reference Spur. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (4) (2023)
Ting-Hsun Wang, Zhuhao Li, Bo Liang, Yu Cai, Zhiyu Wang, Changgui Yang, Yuxuan Luo, Jiabao Sun, Xuesong Ye, Yong Chen, Bo Zhao
A Power-Harvesting CGM Chiplet Featuring Silicon-Based Enzymatic Glucose Sensor. EMBC (2022)
Jack Kee Yong, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Gabriel Chong, Saad Mekhilef, Yong Chen, Pui-In Mak, Rui Paulo Martins
Subthreshold 3-Stage Dual-Branch Charge Pump With 43.4% Peak Power Conversion Efficiency Using Advanced Dynamic Gate-Bias. IEEE Trans. Circuits Syst. II Express Briefs 69 (9) (2022)
Zunsong Yang, Yong Chen, Jia Yuan, Pui-In Mak, Rui Paulo Martins
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM. IEEE Trans. Very Large Scale Integr. Syst. 30 (2) (2022)
Qirui Ren, Chengying Chen, Danian Dong, Xiaoxin Xu, Yong Chen, Feng Zhang
A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection. Sensors 22 (16) (2022)
Yong Chen, Pui-In Mak, Rui Paulo Martins
High-Performance Harmonic-Rich Single-Core VCO With Multi-LC Tank: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 69 (7) (2022)
Zhiyang Zhang, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma
A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE. APCCAS (2022)
Mengdi Zhang, Ye Zhao, Yong Chen, Paolo Crovetti, Yanji Wang, Xinshun Ning, Shushan Qiao
Correction: Zhang et al. A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components. Sensors 2022, 22, 5852. Sensors 22 (22) (2022)
Qiwen Liao, Yuguang Zhang, Siyuan Ma, Lei Wang, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Xi Xiao, Nan Qi
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR. IEEE J. Solid State Circuits 57 (3) (2022)
Qihui Zhang, Ning Ning, Zhong Zhang, Jing Li, Kejun Wu, Yong Chen, Qi Yu
A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration. IEEE J. Solid State Circuits 57 (7) (2022)
Ziyi Chang, Yunshan Zhang, Changgui Yang, Yuxuan Luo, Sijun Du, Yong Chen, Bo Zhao
A Crystal-Less Clock Generation Technique for Battery-Free Wireless Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Paolo Crovetti, Roberto Rubino, Pedro Toledo, Francesco Musolino, Hamilton Klimach, Yong Chen, Anna Richelli
, 0.4V-VDD, 4.5nW-Power DC-Coupled Digital Acquisition Front-End Based on Time-Multiplexed Digital Differential Amplification. ESSCIRC (2022)
Wen Xun Lian, Harikrishnan Ramiah, Gabriel Chong, Kishore Kumar Pakkirisami Churchill, Nai Shyan Lai, Yong Chen, Pui-In Mak, Rui Paulo Martins
A -20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN. IEEE Trans. Very Large Scale Integr. Syst. 30 (11) (2022)
Xinyi Ge, Yong Chen, Lin Wang, Nan Qi, Pui-In Mak, Rui Paulo Martins
A 28-Gb/s 13.8-mW Half-Rate Bang-Bang Clock and Data Recovery Circuit Using Return-to-Zero-Based Symmetrical Bang-Bang Phase Detector. NorCAS (2022)
Yihong Li, Sikai Chen, Yunqi Yang, Qianli Ma, Ming Zhong, Ziyi Lin, Leliang Li, Guike Li, Zhao Zhang, Liyuan Liu, Jian Liu, Nanjian Wu, Yong Chen, Qi Peng, Nan Qi
A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS. APCCAS (2022)
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS. IEEE J. Solid State Circuits 57 (2) (2022)
Tianxiang Wu, Xi Wang, Yong Chen, Junyan Ren, Shunli Ma
A 10-MHz to 50-GHz low-jitter multiphase clock generator for high-speed oscilloscope in 0.15-μm GaAs technology. Int. J. Circuit Theory Appl. 50 (2) (2022)
Zhaoyu Zhang, Xinyu Shen, Yixi Li, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Zhao Zhang
6-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop. APCCAS (2022)
Xiangdong Feng, Yunshan Zhang, Yangfan Xuan, Zhuhao Li, Changgui Yang, Xin Xie, Yuxuan Luo, Xiangwei Zhao, Yong Chen, Bo Zhao
A Square-Wave Stimulated DNA Analyzer Chip Featuring 120μW Power Consumption and Simultaneous Dual-Frequency Detection. IEEE Trans. Circuits Syst. II Express Briefs 69 (10) (2022)
Tan Yee Chyan, Harikrishnan Ramiah, Sharifah Wan Muhamad Hatta, Nai Shyan Lai, Chee-Cheow Lim, Yong Chen, Pui-In Mak, Rui Paulo Martins
Evaluation and Perspective of Analog Low-Dropout Voltage Regulators: A Review. IEEE Access 10 (2022)
Zhiyang Zhang, Lihe Nie, Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma
A 23- to 28-GHz 5-bit switch-type phase shifter with 1-bit calibration based on optimized ABCD matrix design methods for 5G MIMO system in 0.15-μm GaAs. Int. J. Circuit Theory Appl. 50 (6) (2022)
Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins
A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme. ICECS 2022 (2022)
Jian He, Yuguang Zhang, Han Liu, Qiwen Liao, Zhao Zhang, Miaofeng Li, Fan Jiang, Jingbo Shi, Jian Liu, Nanjian Wu, Yong Chen, Patrick Yin Chiang, Ningmei Yu, Xi Xiao, Nan Qi
A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (3) (2022)
Alexander Choo Chia Chun, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Yong Chen, Saad Mekhilef, Pui-In Mak, Rui Paulo Martins
FoM for RF-Based Hybrid Energy Harvesting. IEEE Trans. Very Large Scale Integr. Syst. 30 (10) (2022)
Yixi Li, Xinyu Shen, Zhaoyu Zhang, Guike Li, Tao Yin, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Zhao Zhang
O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL. APCCAS (2022)
Mengdi Zhang, Ye Zhao, Yong Chen, Paolo Crovetti, Yanji Wang, Xinshun Ning, Shushan Qiao
A 7.4-Bit ENOB 600 MS/s FPGA-Based Online Calibrated Slope ADC without External Components. Sensors 22 (15) (2022)
Jian He, Donglai Lu, Haiyun Xue, Sikai Chen, Han Liu, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Liyuan Liu, Nanjian Wu, Ningmei Yu, Fengman Liu, Xi Xiao, Yong Chen, Nan Qi
Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (11) (2022)
Jincheng Zhang, Lihe Nie, Yong Chen, Junyan Ren, Shunli Ma
and 42% PAE. IEEE Trans. Circuits Syst. II Express Briefs 69 (11) (2022)
Ziyi Chang, Changgui Yang, Yunshan Zhang, Zhuhao Li, Tianyu Zheng, Yuxuan Luo, Shaomin Zhang, Kedi Xu, Gang Pan, Bo Zhao, Yong Chen
A Battery-Less Crystal-Less 49.8µW Neural-Recording Chip Featuring Two-Tone RF Power Harvesting. CICC (2022)
Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, Rui Paulo Martins
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS. IEEE J. Solid State Circuits 57 (5) (2022)
Tian Siang Ho, Harikrishnan Ramiah, Kishore Kumar Pakkirisami Churchill, Yong Chen, Chee-Cheow Lim, Nai Shyan Lai, Pui-In Mak, Rui Paulo Martins
Low Voltage Switched-Capacitive-Based Reconfigurable Charge Pumps for Energy Harvesting Systems: An Overview. IEEE Access 10 (2022)
Yong Chen, Harikrishnan Ramiah
APCCAS 2021 Guest Editorial. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (11) (2022)
Kishore Kumar Pakkirisami Churchill, Harikrishnan Ramiah, Gabriel Chong, Yong Chen, Pui-In Mak, Rui Paulo Martins
A Fully-Integrated Ambient RF Energy Harvesting System with 423-μW Output Power. Sensors 22 (12) (2022)
Wenyang Liu, Tianxiang Wu, Tianyang Yan, Fan Yang, Yong Chen, Shunli Ma
A 26-38GHz Ultra-Wideband Balanced Frequency Doubler in 0.15µ m GaAs pHEMT Process. APCCAS (2022)
Hao Guo, Yong Chen, Chaowei Yang, Pui-In Mak, Rui Paulo Martins
A Millimeter-Wave CMOS VCO Featuring a Mode-Ambiguity-Aware Multi-Resonant-RLCM Tank. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
Yunbo Huang, Yong Chen, Pui-In Mak, Rui Paulo Martins
A 3.52-GHz Harmonic-Rich-Shaping VCO with Noise Suppression and Circulation, Achieving -151-dBc/Hz Phase Noise at 10-MHz Offset. ISCAS (2021)
Siyuan Yang, Songyi Li, Jiayan Wu, Yong Chen, Zhenyu Liu
An accelerated architecture of change-point detection for FMCW radar mutual interference based on FPGA. Int. J. Circuit Theory Appl. 49 (11) (2021)
Dong Wei, Tianxiang Wu, Shunli Ma, Yong Chen, Junyan Ren
A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio. ESSCIRC (2021)
Donglai Lu, Jian He, Weizhong Li, Sikai Chen, Jian Liu, Nanjian Wu, Ningmei Yu, Liyuan Liu, Yong Chen, Xi Xiao, Nan Qi
100Gb/s PAM-4 VCSEL Driver and TIA for Short-Reach 400G-1.6T Optical Interconnects. APCCAS (2021)
Lingshan Kong, Yong Chen, Haohong Yu, Chirn Chye Boon, Pui-In Mak, Rui Paulo Martins
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. IEEE Access 9 (2021)
Mingyang You, Minjia Chen, Yihong Li, Guike Li, Jian Liu, Yong Chen, Yingtao Li, Nan Qi
A 4×25Gb/s De-Serializer with Baud-Rate Sampling CDR and Standing-Wave Clock Distribution for NIC Optical Interconnects. ICTA (2021)
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (1) (2021)
Yunbo Huang, Yong Chen, Hailong Jiao, Pui-In Mak, Rui Paulo Martins
A 3.36-GHz Locking-Tuned Type-I Sampling PLL With -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques. IEEE Trans. Circuits Syst. II Express Briefs 68 (9) (2021)
Jincheng Zhang, Tianxiang Wu, Yong Chen, Junyan Ren, Shunli Ma
A 3-to-78GHz Differential Distributed Amplifier with Ultra- Balanced Active Balun and Gain Boosting Techniques in 65-nm CMOS Process. A-SSCC (2021)
Rui Paulo Martins, Pui-In Mak, Chi-Hang Chan, Jun Yin, Yan Zhu, Yong Chen, Yan Lu, Man-Kay Law, Sai-Weng Sin
Bird's-eye view of analog and mixed-signal chips for the 21st century. Int. J. Circuit Theory Appl. 49 (3) (2021)
Ming Zhong, Qingwen Wang, Yong Chen, Jian Liu, Liyuan Liu, Xinghua Wang, Xiaoming Xiong, Nan Qi
A 4×25-Gb/s Serializer with Integrated CDR and 3-Tap FFE Driver for NIC Optical Interconnects. ICTA (2021)
Manxin Li, Yuting Yao, Biao Hu, Jipeng Wei, Yong Chen, Shunli Ma, Fan Ye, Junyan Ren
A 6.94-fJ/Conversion-Step 12-bit 100-MS/s Asynchronous SAR ADC Exploiting Split-CDAC in 65-nm CMOS. IEEE Access 9 (2021)
Zunsong Yang, Yong Chen, Pui-In Mak, Rui Paulo Martins
-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (6) (2021)
Selvakumar Mariappan, Jagadheswaran Rajendran, Yong Chen, Pui-In Mak, Rui Paulo Martins
A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-Distorter (DAAPD) Reconfigurable Linearization Technique. IEEE Trans. Circuits Syst. II Express Briefs 68 (11) (2021)
Hao Guo, Yong Chen, Pui-In Mak, Rui Paulo Martins
PN Corner Without Harmonic Tuning. ISSCC (2021)
Jincheng Zhang, Tianxiang Wu, Lihe Nie, Shunli Ma, Yong Chen, Junyan Ren
for Sub-THz Imaging System. IEEE Access 9 (2021)
Yunbo Huang, Yong Chen, Hao Guo, Pui-In Mak, Rui Paulo Martins
A 3.3-mW 25.2-to-29.4-GHz Current-Reuse VCO Using a Single-Turn Multi-Tap Inductor and Differential-Only Switched-Capacitor Arrays With a 187.6-dBc/Hz FOM. IEEE Trans. Circuits Syst. (11) (2020)
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS. CICC (2020)
Yong Chen, Pui-In Mak, Chirn Chye Boon, Rui Paulo Martins
45.4-GHz-Bandwidth Unity-Gain Output Driver with SDD22<-10dB up to 35 GHz. MWSCAS (2020)
Zunsong Yang, Yong Chen, Shiheng Yang, Pui-In Mak, Rui Paulo Martins
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector. IEEE Access 8 (2020)
Lingshan Kong, Yong Chen, Haohong Yu, Quan Pan, Chirn Chye Boon, Pui-In Mak, Rui Paulo Martins
Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. APCCAS (2019)
Yong Chen, Pui-In Mak, Zunsong Yang, Chirn Chye Boon, Rui Paulo Martins
-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2019)
Hao Guo, Yong Chen, Pui-In Mak, Rui Paulo Martins
A 0.08mm2 25.5-to-29.9GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6dBc/Hz FoM and 130kHz 1/f3 PN Corner. ISSCC (2019)
Arya Balachandran, Yong Chen, Chirn Chye Boon
A 32-Gb/s 3.53-mW/Gb/s Adaptive Receiver AFE Employing a Hybrid CTLE, Edge-DFE and Merged Data-DFE/CDR in 65-nm CMOS. APCCAS (2019)
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS. APCCAS (2019)
Zunsong Yang, Yong Chen, Shiheng Yang, Pui-In Mak, Rui Paulo Martins
A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur. ISSCC (2019)
Zunsong Yang, Yong Chen, Pui-In Mak, Rui Paulo Martins
440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS. A-SSCC (2019)
Xinyi Ge, Yong Chen, Xiaoteng Zhao, Pui-In Mak, Rui Paulo Martins
Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter. IEEE Trans. Very Large Scale Integr. Syst. 27 (10) (2019)
Haohong Yu, Yong Chen, Chirn Chye Boon, Chenyang Li, Pui-In Mak, Rui Paulo Martins
0.5-to-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB. IEEE Trans. Circuits Syst. II Express Briefs (1) (2019)
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
Cell. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2019)
Arya Balachandran, Yong Chen, Chirn Chye Boon
0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26 (3) (2018)
Yong Chen, Pui-In Mak, Chirn Chye Boon, Rui Paulo Martins
A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2018)
Lingshan Kong, Yong Chen, Chirn Chye Boon, Pui-In Mak, Rui Paulo Martins
A Wideband Inductorless dB-Linear Automatic Gain Control Amplifier Using a Single-Branch Negative Exponential Generator for Wireline Applications. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Yong Chen, Pui-In Mak, Yan Wang
A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable for 10-Gb/s I/O Links. IEEE Trans. Very Large Scale Integr. Syst. 23 (5) (2015)
Yong Chen, Pui-In Mak, Li Zhang, He Qian, Yan Wang
Die Size in 90-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (1) (2013)
Yong Chen, Pui-In Mak, Stefano D'Amico, Li Zhang, He Qian, Yan Wang
Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth-Power Scalability. IEEE Trans. Circuits Syst. II Express Briefs (11) (2013)

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Yong Chen