A 6-to-38Gb/s capture-range bang-bang clock and data recovery circuit with deliberate-current-mismatch frequency detection and interpolation-based multiphase clock generation.
Lin WangYong ChenChaowei YangXionghui ZhouMei HanCrovetti Paolo StefanoPui-In MakRui Paulo MartinsPublished in: Int. J. Circuit Theory Appl. (2023)
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