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A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS.

Xiaoteng ZhaoYong ChenLin WangPui-In MakFranco MalobertiRui Paulo Martins
Published in: IEEE J. Solid State Circuits (2022)
Keyphrases
  • high speed
  • low voltage
  • low power
  • cmos technology
  • database
  • low cost
  • random access memory