Xiaoteng Zhao

Publication Activity (10 Years)

Years Active: 2019-2024
Publications (10 Years): 15

Top Topics

Microscopic Images

Occurrence Frequency

Leakage Current

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Microelectron. J.

IEEE J. Solid State Circuits

Publications

Rong Zhou, Linwei Wang, Jianhang Yang, Zhen Li, Xiaoteng Zhao, Shubin Liu
A 8.1-nW, 4.22-kHz, -40-85 °C relaxation oscillator with subthreshold leakage current compensation and forward body bias buffer for low power IoT applications. Microelectron. J. 144 (2024)
Depeng Sun, Ruiqing Wang, Feng Bu, Yuan Gao, Xiaoteng Zhao, Ruixue Ding, Shubin Liu, Rong Zhou
A low-noise, 0.05-17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators. Microelectron. J. 146 (2024)
Rong Zhou, Jianhang Yang, Linwei Wang, Xiaoteng Zhao, Shubin Liu, Depeng Sun
A wideband low power RF Receiver Front-End for Internet-of-Things applications. Microelectron. J. 144 (2024)
Zhicheng Dong, Xiaoteng Zhao, Weitan Huang, Yuan Gao, Depeng Sun, Shubin Liu, Lihong Yang, Zhangming Zhu
Area. ISCAS (2024)
Depeng Sun, Linguo Huang, Rong Zhou, Feng Bu, Lisheng Chen, Xiaoteng Zhao, Ruixue Ding, Shubin Liu, Zhangming Zhu
. IEEE Trans. Circuits Syst. II Express Briefs 71 (4) (2024)
Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (7) (2023)
Zhicheng Dong, Shubin Liu, Xiaoteng Zhao, Baotian Hao, Hongzhi Liang, Haolin Han, Menghao Wang, Weijie Han, Zhangming Zhu
36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply. CICC (2023)
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS. IEEE J. Solid State Circuits 57 (2) (2022)
Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins
A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme. ICECS 2022 (2022)
Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, Rui Paulo Martins
A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS. IEEE J. Solid State Circuits 57 (5) (2022)
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (1) (2021)
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS. CICC (2020)
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS. APCCAS (2019)
Xinyi Ge, Yong Chen, Xiaoteng Zhao, Pui-In Mak, Rui Paulo Martins
Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter. IEEE Trans. Very Large Scale Integr. Syst. 27 (10) (2019)
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins
Cell. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2019)