Login / Signup

A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS.

Xiaoteng ZhaoYong ChenPui-In MakRui Paulo Martins
Published in: APCCAS (2019)
Keyphrases