Feng Zhang

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 33

Top Topics

Tracking Scheme

Random Access Memory

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Yiyang Yuan, Yiming Yang, Xinghua Wang, Xiaoran Li, Cailian Ma, Qirui Chen, Meini Tang, Xi Wei, Zhixian Hou, Jialiang Zhu, Hao Wu, Qirui Ren, Guozhong Xing, Pui-In Mak, Feng Zhang
34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC. ISSCC (2024)
Hao Wu, Yong Chen, Yiyang Yuan, Jinshan Yue, Xiangqu Fu, Qirui Ren, Qing Luo, Pui-In Mak, Xinghua Wang, Feng Zhang
A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (2) (2024)
Shengzhe Yan, Jinshan Yue, Chaojie He, Zi Wang, Zhaori Cong, Yifan He, Mufeng Zhou, Wenyu Sun, Xueqing Li, Chunmeng Dou, Feng Zhang, Huazhong Yang, Yongpan Liu, Ming Liu
A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture. IEEE J. Solid State Circuits 59 (8) (2024)
Wang Ye, Linfang Wang, Zhidao Zhou, Junjie An, Weizeng Li, Hanghang Gao, Zhi Li, Jinshan Yue, Hongyang Hu, Xiaoxin Xu, Jianguo Yang, Jing Liu, Dashan Shang, Feng Zhang, Jinghui Tian, Chunmeng Dou, Qi Liu, Ming Liu
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference. IEEE J. Solid State Circuits 58 (10) (2023)
Xiangqu Fu, Qirui Ren, Hao Wu, Feibin Xiang, Qing Luo, Jinshan Yue, Yong Chen, Feng Zhang
ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Qirui Ren, Qiang Huo, Zhisheng Chen, Qi Gao, Yiming Wang, Yiming Yang, Hao Wu, Xiangqu Fu, Xiaoxin Xu, Qing Luo, Jianfeng Gao, Chengying Chen, Xiaojin Zhao, Dengyun Lei, Xinghua Wang, Feng Zhang, Yong Chen, Pui-In Mak
A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF. IEEE Trans. Very Large Scale Integr. Syst. 31 (2) (2023)
Jinshan Yue, Chaojie He, Zi Wang, Zhaori Cong, Yifan He, Mufeng Zhou, Wenyu Sun, Xueqing Li, Chunmeng Dou, Feng Zhang, Huazhong Yang, Yongpan Liu, Ming Liu
A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture. ISSCC (2023)
Qirui Ren, Chengying Chen, Danian Dong, Xiaoxin Xu, Yong Chen, Feng Zhang
A 13 µW Analog Front-End with RRAM-Based Lowpass FIR Filter for EEG Signal Detection. Sensors 22 (16) (2022)
Linfang Wang, Wang Ye, Chunmeng Dou, Xin Si, Xiaoxin Xu, Jing Liu, Dashan Shang, Jianfeng Gao, Feng Zhang, Yongpan Liu, Meng-Fan Chang, Qi Liu
Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control. IEEE Trans. Circuits Syst. II Express Briefs 68 (5) (2021)
Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Qiao Wang, Haijun Jiang, Jie Yu, Danian Dong, Feng Zhang, Hangbing Lv, Ming Liu
Cell Size Using Self-Adaptive Delayed Termination and Multi-Cell Reference. ISSCC (2021)
Qingting Ding, Tiancheng Gong, Jie Yu, Xiaoxin Xu, Xiaoyan Li, Hangbing Lv, Jianguo Yang, Qing Luo, Peng Yuan, Feng Zhang, Ming Liu
Investigation of weight updating modes on oxide-based resistive switching memory synapse towards neuromorphic computing applications. Sci. China Inf. Sci. 64 (11) (2021)
Qiang Zhao, Wenhan Zheng, Xiaojin Zhao, Yuan Cao, Feng Zhang, Man-Kay Law
/Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise. IEEE Trans. Circuits Syst. (11) (2020)
Fei Tan, Yiming Wang, Yiming Yang, Liran Li, Tian Wang, Feng Zhang, Xinghua Wang, Jianfeng Gao, Yongpan Liu
A ReRAM-Based Computing-in-Memory Convolutional-Macro With Customized 2T2R Bit-Cell for AIoT Chip IP Applications. IEEE Trans. Circuits Syst. II Express Briefs (9) (2020)
Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Hangbing Lv, Feng Zhang, Xiaoyang Zeng, Meng-Fan Chang, Ming Liu
using Sneaking Current Suppression and Compensation Techniques. VLSI Circuits (2020)
Qiang Huo, Zhenhua Wu, Weixing Huang, Xingsheng Wang, Geyu Tang, Jiaxin Yao, Yongpan Liu, Feng Zhang, Ling Li, Ming Liu
A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond. CoRR (2019)
Yiming Wang, Yun Li, Haihua Shen, Dongyu Fan, Wei Wang, Ling Li, Qi Liu, Feng Zhang, Xinghua Wang, Meng-Fan Chang, Ming Liu
A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs (4) (2019)
Wei Zhao, Haihua Shen, Feng Zhang, Huazhe Tan
Adaptive Power Optimization for Mobile Traffic Based on Machine Learning. CSCWD (2019)
Feng Zhang, Linan Li, Qiang Huo, Cong Fang, Wenqiang Ba
A Fluctuation Model of a Hf02 RRAM Cell for Memory Circuit Designs. SMACD (2019)
Qiang Huo, Zhenhua Wu, Feng Zhang, Ling Li
A Modeling Approach for 7nm Technology Node Area-Consuming Circuit Optimization and Beyond. SMACD (2019)
Renjie Lu, Haihua Shen, Feng Zhang, Huawei Li, Wei Zhao, Xiaowei Li
HTDet: A Clustering Method using Information Entropy for Hardware Trojan Detection. CoRR (2019)
Chengying Chen, Liming Chen, Xinghua Wang, Feng Zhang
A 66-dB SNDR, 8-μW analog front-end for ECG/EEG recording application. ISCAS (2018)
Feng Zhang, Dongyu Fan, Qi-Peng Lin, Qiang Huo, Yun Li, Lan Dai, Cheng-Ying Chen, Haihua Shen
The application of non-volatile look-up-table operations based on multilevel-cell of resistance switching random access memory. VLSI-DAT (2018)
Chengying Chen, Liming Chen, Xinghua Wang, Feng Zhang
A 0.6V, 8.4uW AFE circuit for biomedical signal recording. Microelectron. J. 75 (2018)
Haihua Shen, Huazhe Tan, Huawei Li, Feng Zhang, Xiaowei Li
LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection. IEEE Trans. Very Large Scale Integr. Syst. 26 (4) (2018)
Yun Li, Haihua Shen, Ce Li, Feng Zhang
An efficient parity rearrangement coding scheme for RRAM thermal crosstalk effects. ASICON (2017)
Xiaowei Han, Qian Jia, Hongbin Sun, Longfei Wang, Huaqiang Wu, Yimao Cai, Feng Zhang, Yongyi Xie, Fangxu Dong, Xiaoguang Wang, Xiaofei Xue, Li Pang, Xiaoqing Zhao, Mengnan Wu, Pu Bai, Qi Liu, Hangbing Lv, Bing Yu, Chao Zhao, He Qian, Ru Huang, Ming Liu, Yumei Zhou, Nanning Zheng, Qiwei Ren
A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement. CICC (2017)
Nan Qi, Yuhang Kang, Qipeng Lin, Jianxu Ma, Jingbo Shi, Bozhi Yin, Chang Liu, Rui Bai, Shang Hu, Juncheng Wang, Jiangbing Du, Lin Ma, Zuyuan He, Ming Liu, Feng Zhang, Patrick Yin Chiang
A 51Gb/s, 320mW, PAM4 CDR with baud-rate sampling for high-speed optical interconnects. A-SSCC (2017)
Junsheng Lv, You Li, Yumei Zhou, Jianzhong Zhao, Haihua Shen, Feng Zhang
Wide-range tracking technique for process-variation-robust clock and data recovery applications. Frontiers Inf. Technol. Electron. Eng. 18 (5) (2017)
Chengying Chen, Liming Chen, Xinghua Wang, Feng Zhang
A 76μW, 58-dB SNDR analog front-end chip for implantable intraocular pressure detection. ASICON (2017)
Feng Zhang, Dongyu Fan, Yuan Duan, Jin Li, Cong Fang, Yun Li, Xiaowei Han, Lan Dai, Cheng-Ying Chen, Jinshun Bi, Ming Liu, Meng-Fan Chang
A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range. A-SSCC (2017)
Chengying Chen, Liming Chen, Jun Fan, Zenghui Yu, Jun Yang, Xiaoyu Hu, Yong Hei, Feng Zhang
A 1V, 1.1mW mixed-signal hearing aid SoC in 0.13μm CMOS process. ISCAS (2016)
Cheng-Ying Chen, Hongbin Sun, Haihua Shen, Feng Zhang
ReRAM with Novel Double-Reference and Dynamic-Tracking scheme for write yield improvement. IEICE Electron. Express 13 (6) (2016)
Feng Zhang, Hao Ju, Chengying Chen
A PVT variation tolerant and low power 5Gb/s clock and data recovery circuit for PCI-E 2.0/USB 3.0. ASICON (2015)
You Li, Feng Zhang, Yumei Zhou
A novel equalizer for the high-loss backplane at Nyquist frequency. ASICON (2013)
Shuai Chen, Hao Li, Kai Jia, Yue Wang, Xiaobing Shi, Feng Zhang
A fast-lock-in wide-range harmonic-free all-digital DLL with a complementary delay line. ISCAS (2012)
Qihao Liu, Huihui Weng, Feng Zhang, Jianzhong Zhao, Junsheng Lv, You Li
An efficient physical coding sublayer for PCI express in 65nm CMOS. ISPACS (2012)
Rui Bai, Jingguang Wang, Lingli Xia, Feng Zhang, Zongren Yang, Weiwu Hu, Patrick Chiang
Sinusoidal Clock Sampling for Multigigahertz ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2011)
Shuai Chen, Liqiong Yang, Hua Jing, Feng Zhang, Zhuo Gao
A novel SST transmitter with mutually decoupled impedance self-calibration and equalization. ISCAS (2011)
Zhuo Gao, Hang Yu, Patrick Chiang, Yi Yang, Feng Zhang
A 10Gb/s Wire-line Transceiver with Half Rate Period Calibration CDR. ISCAS (2009)
Feng Zhang, Zongren Yang, Wei Feng, Hao Cui, Lingyi Huang, Weiwu Hu
A High Speed CMOS Transmitter and Rail-to-Rail Receiver. DELTA (2008)