An efficient physical coding sublayer for PCI express in 65nm CMOS.

Qihao Liu Huihui Weng Feng Zhang Jianzhong Zhao Junsheng Lv You Li

Published in: ISPACS (2012)

Keyphrases

high speed
coding scheme
low cost
low power
coding method
power consumption
cmos technology
real world
computationally efficient
nm technology
silicon on insulator