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An efficient physical coding sublayer for PCI express in 65nm CMOS.
Qihao Liu
Huihui Weng
Feng Zhang
Jianzhong Zhao
Junsheng Lv
You Li
Published in:
ISPACS (2012)
Keyphrases
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high speed
coding scheme
low cost
low power
coding method
power consumption
cmos technology
real world
computationally efficient
nm technology
silicon on insulator