A 28nm 16.9-300TOPS/W Computing-in-Memory Processor Supporting Floating-Point NN Inference/Training with Intensive-CIM Sparse-Digital Architecture.
Jinshan YueChaojie HeZi WangZhaori CongYifan HeMufeng ZhouWenyu SunXueqing LiChunmeng DouFeng ZhangHuazhong YangYongpan LiuMing LiuPublished in: ISSCC (2023)
Keyphrases
- floating point
- instruction set
- floating point arithmetic
- level parallelism
- memory subsystem
- instruction set architecture
- floating point unit
- training process
- memory bandwidth
- sparse matrices
- neural network
- memory management
- dynamic random access memory
- fixed point
- memory access
- ibm power processor
- bayesian networks
- nearest neighbor
- memory hierarchy
- single instruction multiple data
- knn
- processing elements
- application specific
- training set
- main memory
- multithreading
- operating system
- computer integrated manufacturing
- embedded dram
- parallel architecture
- massively parallel
- sufficient conditions