Zhao Zhang

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 36

Top Topics

Minimax Probability Machine

Phase Locked Loop

Direct Memory Access

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Xinyu Shen, Zhao Zhang, Yong Chen, Yixi Li, Yidan Zhang, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
12.5-16GHz PVT-Tolerant Dual-Path Offset-Charge-Pump-Based Fractional-N PLL Achieving 72.9 fSRMs Jitter, -271.5dB FoMN, and Sub-10% Jitter Variation. CICC (2024)
Li Wang, Zhao Zhang, Can Wang, Rehan Azmat, Weimin Shi, C. Patrick Yue
A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR. IEEE J. Solid State Circuits 59 (2) (2024)
Yang Min, Yi Zhang, Tao Yang, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Nanjian Wu, Yonghui Lin, Huiyao Peng, Jingbo Shi, Nan Qi
A 32Gb/s NRZ Low-Bias DFB Driver with Frequency Boosting for High Efficiency Data Transmission. ISCAS (2024)
Guoqing Wang, Zhao Zhang, Xinyu Shen, Zhaoyu Zhang, Jian Liu, Nanjian Wu, Liyuan Liu
A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process. ICTA (2023)
Zhaoyu Zhang, Zhao Zhang, Yong Chen, Guoqing Wang, Xinyu Shen, Nan Qi, Guike Li, Shuangming Yu, Jian Liu, Nanjian Wu, Liyuan Liu
0.42-pJ/bit 8-32-Gb/s Reference-Less CDR Incorporating Adaptively-Biased ChargeSharing Integrator, Alexander PFD, and 1-Tap DFE. ESSCIRC (2023)
Yixi Li, Zhao Zhang, Yong Chen, Xinyu Shen, Zhao Zhang, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
A 12.75-to-16-GHz Spur-Jitter-Joint-Optimization SS-PLL Achieving -94.55-dBc Reference Spur, 31.9-fs Integrated Jitter and -260.1-dB FoM. A-SSCC (2023)
Yidan Zhang, Zhao Zhang, Yiqing Xu, Xinyu Shen, Nan Qi, Nanjian Wu, Jian Liu, Liyuan Liu
A Wideband Low-Noise Linear LiDAR Analog Front-End Achieving 1.6 GHz Bandwidth, $\boldsymbol{2.7}\ \mathbf{pA}/\mathbf{Hz}^{\boldsymbol{0.5}}$ Input Referred Noise, and 103 $\mathbf{dB}\mathbf{\Omega}$ Transimpedance Gain. A-SSCC (2023)
Han Liu, Nan Qi, Donglai Lu, Zizheng Dong, Zhihan Zhang, Jian He, Guike Li, Leliang Li, Ye Liu, Ziyue Dang, Daigao Chen, Zhao Zhang, Jian Liu, Nanjian Wu, Xi Xiao, Liyuan Liu
A $\boldsymbol{4} \times \boldsymbol{112}-\mathbf{Gb}/\mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics. A-SSCC (2023)
Sikai Chen, Mingyang You, Yunqi Yang, Ye Jin, Ziyi Lin, Yihong Li, Leliang Li, Guike Li, Yujun Xie, Zhao Zhang, Binhao Wang, Ningfeng Tang, Faju Liu, Zheyu Fang, Jian Liu, Nanjian Wu, Yong Chen, Liyuan Liu, Ninghua Zhu, Ming Li, Nan Qi
A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (11) (2023)
Zhao Zhang, Xinyu Shen, Zhaoyu Zhang, Guike Li, Nan Qi, Jian Liu, Yong Chen, Nanjian Wu, Liyuan Liu
A O.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL Achieving 236.6fsrms Jitter, -253.8dB Jitter-Power FoM, and -76.1dBc Reference Spur. ISSCC (2023)
Xinyu Shen, Zhao Zhang, Guike Li, Yong Chen, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu
A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM. ESSCIRC (2023)
Xiangyu Meng, Wang Xie, Jiaqi Zhang, Zhao Zhang
A 0.2-7.1-Gb/s Low-Jitter Full-Rate Reference-Less CDR for Communication Signal Analyzers. IEEE Trans. Instrum. Meas. 72 (2023)
Qiwen Liao, Yuguang Zhang, Siyuan Ma, Lei Wang, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Xi Xiao, Nan Qi
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR. IEEE J. Solid State Circuits 57 (3) (2022)
Sikai Chen, Jintao Xue, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Liyuan Liu, Binhao Wang, Yingtao Li, Nan Qi
A 224-Gb/s Inverter-Based TIA with Interleaved Active-Feedback and Distributed Peaking in 28-nm CMOS for Silicon Photonic Receivers. ICTA (2022)
Yihong Li, Sikai Chen, Yunqi Yang, Qianli Ma, Ming Zhong, Ziyi Lin, Leliang Li, Guike Li, Zhao Zhang, Liyuan Liu, Jian Liu, Nanjian Wu, Yong Chen, Qi Peng, Nan Qi
A 50-Gb/s NRZ Receiver Targeting Low-Latency Multi-Chip Module Optical I/O in 45-nm SOI CMOS. APCCAS (2022)
Zhaoyu Zhang, Xinyu Shen, Yixi Li, Guike Li, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Zhao Zhang
6-to-20-Gb/s NRZ Bang-Bang Clock and Data Recovery Circuit With Dual-Path Loop. APCCAS (2022)
Jian He, Yuguang Zhang, Han Liu, Qiwen Liao, Zhao Zhang, Miaofeng Li, Fan Jiang, Jingbo Shi, Jian Liu, Nanjian Wu, Yong Chen, Patrick Yin Chiang, Ningmei Yu, Xi Xiao, Nan Qi
A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (3) (2022)
Yixi Li, Xinyu Shen, Zhaoyu Zhang, Guike Li, Tao Yin, Nan Qi, Jian Liu, Nanjian Wu, Liyuan Liu, Yong Chen, Zhao Zhang
O.7-V 31.654-μW BPSK Demodulator Incorporating Dual-Path Loop Self-Biased PLL. APCCAS (2022)
Jian He, Donglai Lu, Haiyun Xue, Sikai Chen, Han Liu, Leliang Li, Guike Li, Zhao Zhang, Jian Liu, Liyuan Liu, Nanjian Wu, Ningmei Yu, Fengman Liu, Xi Xiao, Yong Chen, Nan Qi
Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (11) (2022)
Qiwen Liao, Miaofeng Li, Zhao Zhang, Jian Liu, Nanjian Wu, Xi Xiao, Nan Qi
A 50Gb/s High-Efficiency Si-Photonic Transmitter With Lump-Segmented MZM and Integrated PAM4 CDR. CICC (2021)
Tong Fang, Min Liu, Liyuan Liu, Ziteng Cai, Runjiang Dou, Peng Feng, Nan Qi, Zhao Zhang, Jian Liu, Nanjian Wu
A 32×32 Array Terahertz Sensor in 65-nm CMOS Technology. ICTA (2021)
Can Wang, Li Wang, Zhao Zhang, Milad Kalantari Mahmoudabadi, Weimin Shi, C. Patrick Yue
A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects. IEEE Open J. Circuits Syst. 2 (2021)
Zhao Zhang, Guang Zhu, C. Patrick Yue
A 0.25-0.4-V, Sub-0.11-mW/GHz, 0.15-1.6-GHz PLL Using an Offset Dual-Path Architecture With Dynamic Charge Pumps. IEEE J. Solid State Circuits 56 (6) (2021)
Junfeng Hu, Zhao Zhang, Quan Pan
A 15-Gb/s 0.0037-mm² 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator. IEEE Trans. Circuits Syst. II Express Briefs (9) (2020)
Zhao Zhang, Guang Zhu, C. Patrick Yue
Integrated Jitter and -256.4-dB FoM. IEEE J. Solid State Circuits 55 (6) (2020)
Zhao Zhang, Guang Zhu, Can Wang, Li Wang, C. Patrick Yue
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator. IEEE J. Solid State Circuits 55 (10) (2020)
Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu
An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2019)
Qian Di, Zhongxing Zhang, Honglong Li, Zhao Zhang, Peng Feng, Nanjian Wu
Single event upset failure probability evaluation and periodic scrubbing techniques for hierarchical parallel vision processors. IEICE Electron. Express 16 (21) (2019)
Jincheng Yang, Zhao Zhang, Nan Qi, Liyuan Liu, Jian Liu, Nanjian Wu
A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits. Sci. China Inf. Sci. 62 (6) (2019)
Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu
0.1-5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application. IET Circuits Devices Syst. 13 (7) (2019)
Zhao Zhang, Jincheng Yang, Liyuan Liu, Nan Qi, Peng Feng, Jian Liu, Nanjian Wu
A Fast Auto-Frequency Calibration Technique for Wideband PLL with Wide Reference Frequency Range. A-SSCC (2018)
Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu
A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique. IEEE Trans. Very Large Scale Integr. Syst. 26 (5) (2018)
Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu
A 18-to-23 GHz -253.5dB-FoM sub-harmonically injection-locked ADPLL with ILFD aided adaptive injection timing alignment technique. A-SSCC (2017)
Zhao-yang Liu, Liyuan Liu, Zhao Zhang, Jian Liu, Nanjian Wu
Terahertz detector for imaging in 180-nm standard CMOS process. Sci. China Inf. Sci. 60 (8) (2017)
Zhao Zhang, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu
A 1.25-to-6.25 GHz -237.2-dB FOM wideband self-biased PLL for multi-rate serial link data transmitter. IEICE Electron. Express 14 (11) (2017)
Zhao Zhang, Liyuan Liu, Peng Feng, Nanjian Wu
A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Jincheng Yang, Zhao Zhang, Peng Feng, Liyuan Liu, Nanjian Wu
A 1-V 5.2-5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS. ASICON (2015)
Zhao Zhang, Liyuan Liu, Nanjian Wu
A novel 2.4-to-3.6 GHz wideband subharmonically injection-locked PLL with adaptively-aligned injection timing. A-SSCC (2014)