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A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process.

Guoqing WangZhao ZhangXinyu ShenZhaoyu ZhangJian LiuNanjian WuLiyuan Liu
Published in: ICTA (2023)
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