Login / Signup
A 64-Gb/s 0.33-pJ/bit PAM4 Receiver Analog Front-End with a Single-Stage Triple-Peaking CTLE Achieving 22.5-dB Boost in 40-nm CMOS Process.
Guoqing Wang
Zhao Zhang
Xinyu Shen
Zhaoyu Zhang
Jian Liu
Nanjian Wu
Liyuan Liu
Published in:
ICTA (2023)
Keyphrases
</>
single stage
multistage
inventory systems
stochastic optimization
high speed
lost sales
max min
lead time
analog to digital converter
lot sizing
network flow
noise ratio
setup cost
transportation problem
search space
low power
decision makers
graphical models
scheduling problem