A 4-12.1-GHz Fractional-N Ring Sampling PLL Based on Adaptively-Biased PD-Merged DTC Achieving -37.6± 0.9-dBc Integrated Phase Noise, 261.9-fs RMS Jitter, and -240.6-dB FoM.
Xinyu ShenZhao ZhangGuike LiYong ChenNan QiJian LiuNanjian WuLiyuan LiuPublished in: ESSCIRC (2023)