A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique.
Zhao ZhangJincheng YangLiyuan LiuPeng FengJian LiuNanjian WuPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2018)
Keyphrases
- low power
- power consumption
- mixed signal
- low voltage
- high speed
- cmos technology
- power management
- low cost
- energy efficiency
- energy dissipation
- single chip
- energy saving
- data center
- low power consumption
- real time
- digital signal processing
- power reduction
- power dissipation
- multi channel
- logic circuits
- design considerations
- dielectric constant
- video streaming
- frame rate
- signal to noise ratio
- computer vision