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A 1-V 5.2-5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS.
Jincheng Yang
Zhao Zhang
Peng Feng
Liyuan Liu
Nanjian Wu
Published in:
ASICON (2015)
Keyphrases
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high speed
high noise
phase locked loop
low signal to noise ratio
power consumption
sampled data
random sampling
random noise
power supply
missing data
real time
sampling methods
noise level
analog vlsi
circuit design
low power
noise reduction
signal to noise ratio
noisy data
end to end
high frequency
multiresolution