Sign in
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator.
Zhao Zhang
Guang Zhu
Can Wang
Li Wang
C. Patrick Yue
Published in:
IEEE J. Solid State Circuits (2020)
Keyphrases
</>
high speed
shift register
piecewise constant
detection algorithm
power consumption
pseudorandom
high quality
level set
genetic algorithm
integer arithmetic
neural network
denoising
face recognition
real time
linear model
linear systems
learning phase