A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects.
Can WangLi WangZhao ZhangMilad Kalantari MahmoudabadiWeimin ShiC. Patrick YuePublished in: IEEE Open J. Circuits Syst. (2021)
Keyphrases
- low power
- cmos technology
- high speed
- nm technology
- power dissipation
- power consumption
- low voltage
- low cost
- random access memory
- silicon on insulator
- high power
- single chip
- vlsi architecture
- mixed signal
- analog to digital converter
- digital signal processing
- image sensor
- low power consumption
- vlsi circuits
- logic circuits
- power reduction
- wireless transmission
- gate array
- power management
- delay insensitive
- hardware and software
- digital camera