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A 0.25-0.4-V, Sub-0.11-mW/GHz, 0.15-1.6-GHz PLL Using an Offset Dual-Path Architecture With Dynamic Charge Pumps.
Zhao Zhang
Guang Zhu
C. Patrick Yue
Published in:
IEEE J. Solid State Circuits (2021)
Keyphrases
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power consumption
high speed
frequency band
management system
dynamic environments
database
neural network
dual band
real time
data sets
knowledge base
path planning
software architecture
low power
intel xeon