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Zunsong Yang
ORCID
Publication Activity (10 Years)
Years Active: 2019-2023
Publications (10 Years): 10
Top Topics
High Speed
Monte Carlo
Frequency Band
Type Ii
Top Venues
IEEE Trans. Circuits Syst. I Regul. Pap.
VLSI Technology and Circuits
ICICDT
A-SSCC
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Publications
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Yuyang Zhu
,
Zunsong Yang
,
Zhenyu Cheng
,
Md Shamim Sarker
,
Hiroyasu Yamahara
,
Munetoshi Seki
,
Hitoshi Tabata
,
Tetsuya Iizuka
A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit.
ICICDT
(2023)
Zunsong Yang
,
Masaru Osada
,
Shuowei Li
,
Yuyang Zhu
,
Tetsuya Iizuka
A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load.
VLSI Technology and Circuits
(2023)
Zhenyu Cheng
,
Zunsong Yang
,
Yuyang Zhu
,
Md Shamim Sarker
,
Hiroyasu Yamahara
,
Munetoshi Seki
,
Hitoshi Tabata
,
Tetsuya Iizuka
Design of 1-5 GHz Two-Stage Noise-Canceling Low-Noise Amplifier with gm-boosting Technique for Spin Wave Detection Circuit.
ICICDT
(2023)
Zunsong Yang
,
Yong Chen
,
Jia Yuan
,
Pui-In Mak
,
Rui Paulo Martins
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM.
IEEE Trans. Very Large Scale Integr. Syst.
30 (2) (2022)
Zunsong Yang
,
Zule Xu
,
Masaru Osada
,
Tetsuya Iizuka
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter.
VLSI Technology and Circuits
(2022)
Zunsong Yang
,
Yong Chen
,
Pui-In Mak
,
Rui Paulo Martins
-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
68 (6) (2021)
Zunsong Yang
,
Yong Chen
,
Shiheng Yang
,
Pui-In Mak
,
Rui Paulo Martins
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector.
IEEE Access
8 (2020)
Yong Chen
,
Pui-In Mak
,
Zunsong Yang
,
Chirn Chye Boon
,
Rui Paulo Martins
-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis.
IEEE Trans. Circuits Syst. I Regul. Pap.
(10) (2019)
Zunsong Yang
,
Yong Chen
,
Shiheng Yang
,
Pui-In Mak
,
Rui Paulo Martins
A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur.
ISSCC
(2019)
Zunsong Yang
,
Yong Chen
,
Pui-In Mak
,
Rui Paulo Martins
440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS.
A-SSCC
(2019)