Masaru Osada

Publication Activity (10 Years)

Years Active: 2020-2024
Publications (10 Years): 8

Top Topics

Sampling Strategy

Top Venues

VLSI Technology and Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Yuyang Zhu, Zunsong Yang, Masaru Osada, Haoming Zhang, Tetsuya Iizuka
Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (5) (2024)
Masaru Osada, Zule Xu, Zunsong Yang, Tetsuya Iizuka
A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering. IEEE J. Solid State Circuits 59 (7) (2024)
Zunsong Yang, Masaru Osada, Shuowei Li, Yuyang Zhu, Tetsuya Iizuka
A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load. VLSI Technology and Circuits (2023)
Masaru Osada, Zule Xu, Ryoya Shibata, Tetsuya Iizuka
Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Masaru Osada, Zule Xu, Tetsuya Iizuka
An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering. ESSCIRC (2022)
Zunsong Yang, Zule Xu, Masaru Osada, Tetsuya Iizuka
A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. VLSI Technology and Circuits (2022)
Zule Xu, Masaru Osada, Tetsuya Iizuka
A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur. VLSI Circuits (2021)
Masaru Osada, Zule Xu, Tetsuya Iizuka
A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur. VLSI Circuits (2020)