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An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS.
Jin Zhang
Xiaoqian Ren
Shubin Liu
Chi-Hang Chan
Zhangming Zhu
Published in:
IEEE Trans. Circuits Syst. II Express Briefs (2020)
Keyphrases
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analog to digital converter
power consumption
random access memory
low cost
dynamic environments
high speed
low power
data flow
clock gating
wavelet transform
cmos technology