Ewout Martens

ORCID

Publication Activity (10 Years)

Years Active: 2002-2024
Publications (10 Years): 30

Top Venues

IEEE J. Solid State Circuits

ISSCC

VLSI Circuits

ESSCIRC

Katholieke Universiteit Leuven, Belgium (PHD)

Education History

Katholieke Universiteit Leuven, Belgium

PHD

Publications

Ewout Martens, Adam Cooman, Pratap Tumkur Renukaswamy, Shun Nagata, Sehoon Park, Jorge-Luis Lagos, Nereo Markulic, Jan Craninckx
22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC. ISSCC (2024)
Shun Nagata, Ewout Martens, Adam Cooman, Jan Craninckx
A 28GHz Low Jitter, Low Power Fully Differential Self-Biased Clock Buffer with Embedded Low Pass Filter Utilizing Enable Switch in 16nm FinFET. MWSCAS (2023)
Lucas Moura Santana, Ewout Martens, Jorge Lagos, Piet Wambacq, Jan Craninckx
A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS. ESSCIRC (2023)
Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Rui Paulo Martins, Yan Zhu, Jan Craninckx, Chi-Hang Chan
A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Ewout Martens, Nereo Markulic, Jorge Luis Lagos-Benites, Jan Craninckx
Calibration Techniques for Optimizing Performance of High-Speed ADCs. CICC (2023)
Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS. IEEE J. Solid State Circuits 57 (7) (2022)
Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS. IEEE J. Solid State Circuits 57 (4) (2022)
Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier. IEEE J. Solid State Circuits 57 (6) (2022)
Keigo Bunsen, Ewout Martens, Davide Dermit, Jan Craninckx
A Redundancy-Based Background Calibration for Comparator Offset/Threshold and DAC Gain in a Ping-Pong SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs 68 (2) (2021)
Ewout Martens, Davide Dermit, Mithlesh Shrivas, Shun Nagata, Jan Craninckx
A Compact 8-bit, 8 GS/s 8×TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW. VLSI Circuits (2021)
Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
Asynchronous Event-Driven Clocking and Control in Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (7) (2021)
Lai Wei, Zihao Zheng, Nereo Markulic, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins
Nyquist Zone in 1GS/s ADC. VLSI Circuits (2021)
Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC. ESSCIRC (2021)
Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm. IEEE J. Solid State Circuits 56 (4) (2021)
Jorge Lagos, Nereo Markulic, Benjamin P. Hershberg, Davide Dermit, M. Shrivas, Ewout Martens, Jan Craninckx
A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS. VLSI Circuits (2021)
Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion. IEEE J. Solid State Circuits 56 (8) (2021)
Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. ISSCC (2020)
Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. VLSI Circuits (2020)
Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. IEEE J. Solid State Circuits 54 (3) (2019)
Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx
A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. ISSCC (2019)
Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. ISSCC (2019)
Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. IEEE J. Solid State Circuits 54 (2) (2019)
Nereo Markulic, Pratap Tumkur Renukaswamy, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. IEEE J. Solid State Circuits 54 (4) (2019)
Shiwei Wang, Carolina Mora Lopez, Seyed Kasra Garakoui, Ho Sung Chun, Didac Gomez Salinas, Wim Sijbers, Jan Putzeys, Ewout Martens, Jan Craninckx, Nick Van Helleputte
A Compact Quad-Shank CMOS Neural Probe With 5, 120 Addressable Recording Sites and 384 Fully Differential Parallel Channels. IEEE Trans. Biomed. Circuits Syst. 13 (6) (2019)
Ewout Martens, Benjamin P. Hershberg, Jan Craninckx
A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization. IEEE J. Solid State Circuits 53 (4) (2018)
Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. CICC (2018)
Nereo Markulic, Pratap Renukaswarny, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx
A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS. VLSI Circuits (2018)
Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. IEEE J. Solid State Circuits 51 (12) (2016)
Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx
A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS. IEEE J. Solid State Circuits 51 (7) (2016)
Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. ISSCC (2016)
Barend van Liempd, Saneaki Ariumi, Ewout Martens, Shih-Hung Chen, Piet Wambacq, Jan Craninckx
A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection. ESSCIRC (2015)
Bob Verbruggen, Jorgo Tsouhlarakis, Takaya Yamamoto, Masao Iriguchi, Ewout Martens, Jan Craninckx
A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation. IEEE J. Solid State Circuits 50 (9) (2015)
Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx
-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS. ESSCIRC (2015)
Barend van Liempd, Jonathan Borremans, Ewout Martens, Sungwoo Cha, Hans Suys, Bob Verbruggen, Jan Craninckx
A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration. IEEE J. Solid State Circuits 49 (8) (2014)
Barend van Liempd, Jonathan Borremans, Sungwoo Cha, Ewout Martens, Hans Suys, Jan Craninckx
IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm. CICC (2013)
Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaert
RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. IEEE J. Solid State Circuits 47 (4) (2012)
Ewout Martens, Georges G. E. Gielen
ANTIGONE: Top-down creation of analog-to-digital converter architectures. Integr. 42 (1) (2009)
Ewout Martens, Georges G. E. Gielen
Classification of analog synthesis tools based on their architecture selection mechanisms. Integr. 41 (2) (2008)
Georges G. E. Gielen, Tom Eeckelaert, Ewout Martens, Trent McConaghy
Automated synthesis of complex analog circuits. ECCTD (2007)
Ewout Martens, Georges G. E. Gielen
Generic Behavioral Modeling of Analog and Mixed-Signal Systems. FDL (2006)
Ewout Martens, Georges G. E. Gielen
A behavioral model of sampled-data systems in the phase-frequency transfer domain for architectural exploration of transceivers. ISCAS (2006)
Ewout Martens, Georges G. E. Gielen
Top-down heterogeneous synthesis of analog and mixed-signal systems. DATE (2006)
Ewout Martens, Georges G. E. Gielen
Analyzing continuous-time Delta-Sigma-Modulators with generic behavioral models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (5) (2006)
Ewout Martens, Georges G. E. Gielen
Behavioral modeling and simulation of weakly nonlinear sampled-data systems. ISCAS (3) (2005)
Ewout Martens, Georges G. E. Gielen
Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series. DATE (2005)
Georges G. E. Gielen, Kenneth Francken, Ewout Martens, Martin Vogels
An analytical integration method for the simulation of continuous-time ΔΣ modulators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (3) (2004)
Ewout Martens, Georges G. E. Gielen
High-level modeling of continuous-time Delta-Sigma A/D-converters using formal models. ASP-DAC (2004)
Ewout Martens, Georges G. E. Gielen
A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design. DATE (2004)
Ewout Martens, Georges G. E. Gielen
A Model of Computation for Continuous-Time ?-? Modulators. DATE (2003)
Martin Vogels, Kenneth Francken, Ewout Martens, Georges G. E. Gielen
Efficient time-domain simulation of continuous-time Delta-Sigma A/D converters using analytical integration. ISCAS (4) (2002)
Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen
DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators. DATE (2002)
Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen
A behavioral simulation tool for continuous-time delta sigma modulators. ICCAD (2002)

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Publication Activity (10 Years)

Top Topics

Top Venues

Ewout Martens