Login / Signup
A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization.
Ewout Martens
Benjamin P. Hershberg
Jan Craninckx
Published in:
IEEE J. Solid State Circuits (2018)
Keyphrases
</>
synthetic aperture radar
cmos technology
silicon on insulator
power consumption
sar images
high speed
single chip
analog to digital converter
low cost
metal oxide semiconductor
low power
automatic target recognition
sea ice
nm technology
low voltage
analog vlsi
circuit design
real time