Pratap Tumkur Renukaswamy

Publication Activity (10 Years)

Years Active: 2019-2024
Publications (10 Years): 7

Top Topics

Clock Frequency

Metal Oxide Semiconductor

Parallel Architecture

Top Venues

IEEE J. Solid State Circuits

Publications

Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulic, Jan Craninckx
A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL. IEEE J. Solid State Circuits 59 (6) (2024)
Ewout Martens, Adam Cooman, Pratap Tumkur Renukaswamy, Shun Nagata, Sehoon Park, Jorge-Luis Lagos, Nereo Markulic, Jan Craninckx
22.5 A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC. ISSCC (2024)
Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulic, Veerle Derudder, Dae-Woong Park, Piet Wambacq, Jan Craninckx
A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL. ISSCC (2023)
Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx
Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. ISCAS (2021)
Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx
A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth. IEEE J. Solid State Circuits 55 (12) (2020)
Pratap Tumkur Renukaswamy, Nereo Markulic, Sehoon Park, Anirudh Kankuppe, Qixian Shi, Piet Wambacq, Jan Craninckx
17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth. ISSCC (2020)
Nereo Markulic, Pratap Tumkur Renukaswamy, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. IEEE J. Solid State Circuits 54 (4) (2019)