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Pratap Tumkur Renukaswamy
ORCID
Publication Activity (10 Years)
Years Active: 2019-2023
Publications (10 Years): 5
Top Topics
Metal Oxide Semiconductor
Hurst Exponent
High Speed
Parallel Architecture
Top Venues
ISSCC
IEEE J. Solid State Circuits
ISCAS
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Publications
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Pratap Tumkur Renukaswamy
,
Kristof Vaesen
,
Nereo Markulic
,
Veerle Derudder
,
Dae-Woong Park
,
Piet Wambacq
,
Jan Craninckx
A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL.
ISSCC
(2023)
Pratap Tumkur Renukaswamy
,
Nereo Markulic
,
Piet Wambacq
,
Jan Craninckx
Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation.
ISCAS
(2021)
Pratap Tumkur Renukaswamy
,
Nereo Markulic
,
Piet Wambacq
,
Jan Craninckx
A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth.
IEEE J. Solid State Circuits
55 (12) (2020)
Pratap Tumkur Renukaswamy
,
Nereo Markulic
,
Sehoon Park
,
Anirudh Kankuppe
,
Qixian Shi
,
Piet Wambacq
,
Jan Craninckx
17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth.
ISSCC
(2020)
Nereo Markulic
,
Pratap Tumkur Renukaswamy
,
Ewout Martens
,
Barend van Liempd
,
Piet Wambacq
,
Jan Craninckx
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS.
IEEE J. Solid State Circuits
54 (4) (2019)